Super junction device and corner structure layout design and manufacture process thereof

A super-junction device and layout design technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as insufficient improvement of the overall withstand voltage, and achieve the effect of improving the withstand voltage

Inactive Publication Date: 2016-06-08
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The invention discloses a super junction device corner structure and a super junction device adopting the same. Corresponding structure pattern optimization and adjustment is made on a strip-shaped doping pattern of a second conductivity type in a corner area according to the boundary change of the corner (from a straight line to a curve) to make the area ratio of doping of a first conductivity type to doping of the second conductivity type in the corner area almost the same with the ratio in an ordinary cellular area and to make the charges of impurities of the first conductivity type and the charges of impurities of the second conductivity type balanced, and therefore, the super junction device achieves almost the same withstand voltage as an ordinary cellular area at the corner.

Application Domain

Semiconductor/solid-state device manufacturingSemiconductor devices

Technology Topic

VoltageEngineering +5


  • Super junction device and corner structure layout design and manufacture process thereof
  • Super junction device and corner structure layout design and manufacture process thereof
  • Super junction device and corner structure layout design and manufacture process thereof


  • Experimental program(1)

Example Embodiment

[0045] The present invention will be further explained below in conjunction with the drawings:
[0046] Such as figure 1 with figure 2 As shown, in the corner structure of the super junction device of the present invention, in the corner area, the boundary of the repeating unit of the cell changes from a straight line (a boundary) to a curved line (b boundary), and the second conductivity type doping pattern (shaded Part) will be optimized and adjusted according to the vertical distance between the a boundary and the b boundary, so that the area ratio of the first conductivity type doping to the second conductivity type doping in the B'area is the same as that of the ordinary cell area ( figure 1 The ratio in the A area) is almost the same, so that the super junction device can reach almost the same withstand voltage value as the ordinary cell area at the corner.
[0047] Such as Figure 3-Figure 5 As shown, in the corner structure layout design of the super junction device of the present invention, the optimized area is B'(the area enclosed by auxiliary lines a, b, and c), and the area on the right of auxiliary line c is the repetition of ordinary cells The cell is the ideal N-type doping to P-type doping ratio M, which is also the expected ratio of P-type doping (shaded part) to N-type doping in the B'region.
[0048] Specifically, the layout design steps of the corners are as follows:
[0049] Such as image 3 As shown, the a boundary in the B'area is divided into n segments along the horizontal direction (the larger the n, the closer the segments are connected to the arc, the closer the optimized pattern is to the ideal, but the greater the drawing workload; the more n Smaller, easier to draw, but with lower accuracy) Make vertical auxiliary lines c1, c2, c3, c4, c5, and c6 respectively (6 points are used as an example here, which is not an actual practice. Actually, the method of the present invention needs to be used for optimization Technicians should make a trade-off between the accuracy requirements of their own device characteristics and the corresponding workload to determine the actual number of segments n). Measure the distance L0, L1, L2, L3, L4, L5, L6 between c, c1~c6 and the intersection of a and b. The ideal N-type P-type ratio is a fixed value of M, M=d/(Ld), so d(n)=L(n)*M/(1+M).
[0050] Such as Figure 4 Shown: determine the center point of c1 ~ c6, the center point is vertically offset downward by d(n)/2 to determine the C(n)' point, and the vertical upward offset is d(n)/2 to determine C(n)" Point. Connect the endpoints C', C1', C2', C3', C4', C5', C6' and the intersection of a and b, and connect the endpoints C", C1", C2", C3", C4", C5", C6" and the intersection of a and b are connected to form the optimized doping pattern of the B'region, which can make the first conductivity type impurity doping (such as N type) and the second conductivity type doping (such as The ratio of P type) is always close to the ideal value M (because it is a curve composed of line segments, the ideal ratio cannot be 100%).
[0051] Further, although the optimized pattern obtained through the above steps is close to the ideal P and N doping ratio, the size of the sharp corner portion of the optimized pattern will be smaller than the minimum line width of the actual manufacturing equipment, resulting in the shape of the sharp corner portion. Deformation occurs, so it is necessary to further optimize and improve the sharp corners to meet the actual manufacturing requirements. The improvement methods and steps are as follows:
[0052] Such as Figure 5 Shown: Find the figure with sharp corners less than the minimum line width (the dotted line is the figure before improvement, which can be approximated as an isosceles triangle, point D is the top angle, E and F are the bottom, and the bottom edge of the isosceles triangle is EF The length should be greater than or equal to the minimum width of the machine); then draw the mid-vertical line DG to the base EF of the isosceles triangle; then use the base EF of the isosceles triangle as the width and half the distance of the mid-vertical line DG as the length , Make a rectangle E'F'FE, and replace the isosceles triangle with this rectangle shape. According to the area formula, the area of ​​this rectangle E'F'FE is equal to the area of ​​triangle DEF, so it can be considered that the ratio of P-type doping (shaded part) and N-type doping (blank part) in this local area is different before and after optimization. Change is also close to the design ideal value M. It can not only meet the requirements of constant pressure resistance, but also meet the requirements of actual manufacturing.
[0053] The corner pattern optimized in the previous step is like Image 6 Shown.
[0054] The final manufacturing process of the super junction device of the present invention includes the following steps:
[0055] (1) Prepare a heavily doped substrate, N-type doping, with a resistivity of 0.0001~0.1 ohm·cm;
[0056] (2) Grow an N-type lightly doped epitaxial layer with a resistivity of 1-100 ohm·cm and an epitaxial thickness of T microns (T is about 1-10 microns);
[0057] (3) Use the patterned lithography plate of the present invention to perform a photolithography step, and then perform P-type doping implantation. The implantation impurity is boron element B11, and the implantation dose is about 1E12atom/cm 2 ~1E15atom/cm 2;
[0058] (4) Repeat steps 1-2 and 1-3 n times to make the total thickness Ttotal of the N-type lightly doped epitaxial layer T*n microns, and the thickness of Ttotal is determined according to the withstand voltage required by the super junction device;
[0059] (5) Push the junction through high temperature, the furnace tube temperature is 850 ℃ ~ 1200 ℃, the duration is 30 minutes ~ 300 minutes, activate the P type impurity, after the P type impurity in each lightly doped epitaxial layer diffuses, and the upper and lower The P-type impurities in the epitaxial layer are connected (the thickness T of each epitaxial layer needs to be adjusted so that the P-type impurities can connect between the upper and lower layers); at this time, the substrate of the super junction device is prepared, and 1 to 6 are 6 times of N-type light doping The epitaxial layer, 7 is P-type impurity; so far, the substrate manufacturing steps of the super junction device are completed, such as Figure 7 Shown
[0060] The following process steps of super junction MOS are carried out as follows:
[0061] (6) Growing a local field oxide layer through the LOCOS process (8);
[0062] (7) Carry out N-type impurity implantation, the implantation dose is 1e12atom/cm 2 ~1e15atom/cm 2;
[0063] (8) Grow a gate oxide layer (9) with a thickness of 100A~1200A. This thickness is determined by the breakdown voltage and threshold voltage requirements of general MOS;
[0064] (9) After the gate oxide is grown, N-type polysilicon is grown by low-pressure chemical vapor deposition. Manufacture the gate (10) of the MOS and the floating polysilicon field plate (10') through photolithography and etching steps;
[0065] (10) Carry out P-WELL injection (11) and push the junction at high temperature to activate impurities and make PWELL reach the required depth and lateral diffusion;
[0066] (11) Perform N+ implantation to form the source of the MOS (12), the implant dose is 1e12atom/cm 2 ~5e15atom/cm 2;
[0067] (12) Perform polysilicon gate oxidation with an oxidation thickness of about 60A~1000A;
[0068] (13) Carry out P+ implantation (13), the implant dose is 1e12atom/cm 2 ~5e15atom/cm 2;
[0069] (14) Then deposit TEOS as an inter-level dielectric (15);
[0070] (15) Sputtering or evaporative deposition of aluminum to produce metal contact holes, electrodes (14) and floating metal field plates (14'). So far, the manufacturing steps of the super junction device of the present invention are formed, and the cross-sectional view is as follows Figure 8 Shown.
[0071] The above-mentioned embodiments are only preferred embodiments of the present invention, and do not limit the technical solutions of the present invention. As long as they are technical solutions that can be implemented on the basis of the above-mentioned embodiments without creative work, they shall be regarded as falling into the patent of the present invention. Within the scope of protection of the rights.


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