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A q-gating cell architecture for satisfying the shift-loading (los) test and an algorithm for identifying the best q-gating candidate

A gating and architecture technology, applied in the field of scan-shift power control, which can solve problems such as the existence of scan-shift power problems

Active Publication Date: 2018-11-27
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using Q-strobe to control scan-shift power for the entire design can be problematic

Method used

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  • A q-gating cell architecture for satisfying the shift-loading (los) test and an algorithm for identifying the best q-gating candidate
  • A q-gating cell architecture for satisfying the shift-loading (los) test and an algorithm for identifying the best q-gating candidate
  • A q-gating cell architecture for satisfying the shift-loading (los) test and an algorithm for identifying the best q-gating candidate

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Embodiment Construction

[0015] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods that can be embodied in various forms. However, this invention may be embodied in many different ways and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0016] According to one or more exemplary embodiments described herein, there is provided an optimal approach to Q-gating scan chain designs that eliminates timing issues. The method can also determine the optimal Q-gate structure to support shift loading, and thus ...

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PUM

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Abstract

A method is provided for using multiple flip-flops to create an architecture that supports Q gating for load-on-shift (LOS) scan testing. The method may include applying a common clock signal to each clock input of the plurality of flip-flops, and applying a gating scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include: directly applying a global scan enable signal to each of a plurality of Q gates, each of the plurality of Q gates corresponds to each of the plurality of flip-flops, wherein the global scan The enable signal passes through a signal path that bypasses combinational logic between any two flip-flops of the plurality of flip-flops.

Description

[0001] Cross References to Related Applications [0002] This application is related to the following commonly owned, co-pending U.S. patent application filed on July 6, 2013, the contents and disclosure of which are expressly incorporated herein by reference in its entirety: U.S. Patent Application Serial No. (13 / 942,732), The name is "ALGORITHM TO IDENTIFY BEST Q-GATING CANDIDATES AND A Q-GATING CELLARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT(LOS) TESTING". technical field [0003] The present invention relates generally to integrated circuit testing, and more particularly to control of scan-shift power. Background technique [0004] As transistor geometries shrink with respect to technology in integrated circuits (microelectronic chips or microchips), the number and types of defects on chips increases exponentially with logic density. A defect may be an error introduced into a device during the manufacturing process. A failure model is a mathematical description of how...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318544G01R31/318552
Inventor R·戈帕拉克里希南塞蒂K·库尔施雷施塔B·乌谱图利
Owner INT BUSINESS MASCH CORP