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Method and system for static timing analysis in circuit design

A static timing analysis and circuit design technology, applied in CAD circuit design, computer-aided design, CAD based on constraints, etc., can solve problems such as increasing running time and chip size, not timing violations, and affecting STA accuracy, etc., to achieve The effect of eliminating pessimism, increasing accuracy, and improving efficiency

Active Publication Date: 2019-05-07
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Pessimistic path delay calculations affect STA accuracy and may indicate timing violations that do not realistically occur
For this reason, it will take unnecessary effort to optimize the circuit design, and may increase the run time and die size

Method used

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  • Method and system for static timing analysis in circuit design
  • Method and system for static timing analysis in circuit design
  • Method and system for static timing analysis in circuit design

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Embodiment Construction

[0019] Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0020] figure 1 A block diagram of an exemplary computer system / server 12 suitable for use in implementing embodiments of the invention is shown. figure 1 The computer system / server 12 shown is only an example and should not impose any limitation on the functions and scope of use of the embodiments of the present invention.

[0021] Such as figure 1 As shown, computer system / server 12 takes the form of a general purpose computing device. ...

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Abstract

The present disclosure relates to methods and systems for static timing analysis in circuit design. In one embodiment, a method for calculating path delay in static timing analysis of circuit design is disclosed, comprising: determining the connection relationship between the first device and the second device in the path of the circuit design; The connection relationship generates a delay constraint associated with the first device and the second device, the delay constraint specifying a difference between a first device delay of the first device and a second device delay of the second device ; and calculating a path delay for the path using the first device delay and the second device delay meeting the delay constraints. A corresponding system is also described.

Description

technical field [0001] Embodiments of the present invention relate generally to circuit design, and in particular to methods and systems for static timing analysis in circuit design. Background technique [0002] Static timing analysis (Static Timing Analysis, STA) is an important part in circuit design. A large number of tools and methods for STA have been developed. The main purpose of the STA process is to calculate various timing performance indicators of the circuit design by analyzing the delay of the path, so as to find paths that violate the timing requirements. Calculating the path delay (path delay) of each path in the circuit design is the basis of STA. A path includes one or more devices, such as gates. The delay of a path may be determined based on the delay of devices in the path. The device delay can be determined and stored in advance, for example, in a standard cell library (Standard Cell Library), and can be accessed and used in the STA process. [000...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/3312G06F2119/12G01R31/31725G01R31/31726G06F30/327G06F30/00G06F30/30G06F30/35G06F2111/04G06F30/3315
Inventor 刘洋欧鹏牛佳戴红卫
Owner INT BUSINESS MASCH CORP