fpga chip power-on control method, circuit and fpga chip

Abstract

The invention discloses a field-programmable gate array (FPGA) chip power-on control method and circuit as well as an FPGA chip. The FPGA chip power-on control method comprises the steps: configuring a voltage selector, respectively connecting an input end of the voltage selector with a static random access memory (SRAM) power supply and an FPGA chip internal core module power supply, and respectively connecting an output end of the voltage selector with each SRAM of the FPGA chip; in an FPGA chip power-on process, by the voltage selector, selecting one with a larger output voltage from the SRAM power supply and the FPGA chip internal core module power supply to be as a zero-clearing level for each SRAM, and performing a zero-clearing operation on each SRAM. According to the FPGA chip power-on control method and circuit as well as the FPGA chip, due to configuration of the voltage selector, in the FPGA chip power-on process, zero clearing under a higher level is ensured, and no matter that the higher level is a level output by a core (an internal core module) or a level output by each SRAM, a situation that zero clearing of each SRAM is not completed before power-on of each SRAM is completed can be prevented from occurring, so that the zero-clearing operation can be performed when the power supply voltage is very low; therefore, the power consumption is very low, and the FPGA chip is always in a low power consumption state in the FPGA chip power-on process.

Description

technical field [0001] The invention relates to the field of FPGA chips (Field-Programmable Gate Array, Field Programmable Gate Array), in particular to an FPGA chip power-on control method, circuit and FPGA chip. Background technique [0002] During the power-on process of the FPGA chip, it is necessary to clear the SRAM (Static Random Access Memory, static random access memory) before the power-on is completed. At present, the usual power-on clearing is to directly use the level output by the core (internal core module) inside the FPGA chip as the clearing level to clear the SRAMs inside the FPGA chip. However, SRAM is often powered separately, which is different from the internal power supply, so the power-on speed of SRAM and core may be different. At present, the level output by the core is used as the counting level, and there may be differences in the speed of the independent voltage power-up sequence. If the SRAM power-up is faster, the core (internal core) voltage ...

AI Technical Summary

Problems solved by technology

[0004] The main technical problem to be solved by the present invention is to provide an FPGA chip power-on control method, circuit and FPGA chip to solve the problem of using the level output by the core as the counting level in the power-on process of the existing FPGA chip, which may lead to greater power generation. consumption problem

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