Method of forming a semiconductor device structure having a gate
A device structure and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as component size reduction and difficult implementation of manufacturing processes
Active Publication Date: 2019-05-21
TAIWAN SEMICON MFG CO LTD
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- Description
- Claims
- Application Information
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Problems solved by technology
[0006] However, manufacturing processes continue to become more difficult to implement due to ever-shrinking component sizes
Therefore, it is a challenge to form reliable semiconductor devices with smaller and smaller dimensions
Method used
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Embodiment Construction
[0022] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which a first component may be formed between the first component and the second component. Additional components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the ...
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Abstract
The present invention provides methods for forming semiconductor device structures. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the layer of gate material. The planarization layer includes a first material that is different from the second material of the gate material layer and the third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer to form a gate in the trench. Embodiments of the invention also relate to methods of forming semiconductor device structures having gates.
Description
[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application No. 62 / 096,753, filed December 24, 2014, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention relate to integrated circuit devices and, more particularly, to methods of forming semiconductor device structures having gates. Background technique [0004] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. However, these advances have also increased the complexity of handling and manufacturing ICs. [0005] In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased, while geometry size (ie, the smallest compone...
Claims
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IPC IPC(8): H01L21/336H01L21/28H01L29/78
CPCH01L21/28008H01L29/66068H01L29/66795H01L29/7855H01L21/28123H01L29/517H01L29/66545H01L21/31058H01L21/31144H01L21/823437H01L21/823431H01L21/28088
Inventor 张家玮巫柏奇方文翰
Owner TAIWAN SEMICON MFG CO LTD