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Sample-rate conversion in a multi-clock system sharing a common reference

A sampling rate converter and sampling frequency technology, used in baseband system components, automatic power control, electromagnetic signal storage, etc., can solve the problems of high intermediate conversion frequency and inefficient sampling rate conversion calculation.

Inactive Publication Date: 2016-07-20
MARVELL ASIA PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the ratio of the first sampling frequency to the second sampling frequency is not an integer, the intermediate conversion frequency is high, and thus the sampling rate conversion is not computationally efficient

Method used

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  • Sample-rate conversion in a multi-clock system sharing a common reference
  • Sample-rate conversion in a multi-clock system sharing a common reference
  • Sample-rate conversion in a multi-clock system sharing a common reference

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Embodiment Construction

[0033] Figure 1A A communication device 100 according to an embodiment is shown. The communication device 100 includes an antenna 101, a multiplexer 102, a radio frequency to intermediate frequency (RF to IF) mixer 103, an analog to digital (A / D) converter 104, a digital subsystem 105, a transmitter circuit 106, and a digital to analog (D / A) Converter 107.

[0034] When the antenna 101 receives the RF signal, the multiplexer 102 directs the received RF signal to the RF-to-IF converter 103, and the RF-to-IF converter 103 converts the RF signal into an IF signal. The A / D converter 104 converts the IF signal into a digital signal and outputs the digital signal to the digital subsystem 105 to process the digital signal. The digital subsystem 105 provides the output digital signal to the D / A converter 107 to convert the output signal into an analog signal. The transmitter circuit 106 processes analog signals for radio transmission via the antenna 101 through the multiplexer 102.

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Abstract

A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.

Description

[0001] Cross references to related applications [0002] This disclosure claims the benefits of U.S. Provisional Application No. 61 / 895,024 filed on October 24, 2013, the entire content of which is incorporated herein by reference. Background technique [0003] Electronic devices that transmit and receive different types of signals (such as telecommunication systems) may include multiple signal processing circuits. When a signal processing circuit using the first sampling frequency sends a digital signal to another signal processing circuit using the second sampling frequency, sampling rate conversion is required to change the sampling rate of the digital signal from the first sampling frequency to the second sampling frequency . [0004] The traditional sampling rate conversion method includes converting a digital signal into an analog signal, and then re-sampling the analog signal at a new sampling rate to obtain a new digital signal. However, this method usually uses a digital-t...

Claims

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Application Information

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IPC IPC(8): H03L7/06H03L7/07
CPCH03L7/22H04L25/05H03L7/099
Inventor R·威诺托
Owner MARVELL ASIA PTE LTD