[0025] Hereinafter, the present invention will be described in detail with reference to the drawings and in conjunction with the embodiments. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other if there is no conflict.
[0026] In this embodiment, a method for decoding a data stream is provided, figure 2 Is a flowchart of a method for decoding a data stream according to an embodiment of the present invention, such as figure 2 As shown, the process includes the following steps:
[0027] Step S102, receiving multiple compressed data streams, where the compressed data stream is a data stream using a first encoding method, and the first encoding method needs to be decoded in a serial decoding method;
[0028] Step S104, using multiple decoders to respectively decode the multiple compressed data streams in parallel to obtain multiple decoded data streams;
[0029] Step S106, buffering the multiple-channel decoded data stream;
[0030] Step S108: Perform subsequent decoding processing on the buffered multi-channel decoded data stream in a polling manner.
[0031] Through the above steps, multiple decoders decode multiple compressed data streams in parallel, and perform subsequent decoding processing on the multiple decoded data streams in a polling manner. Compared with the prior art, the decoding process can only be one by one. Serial decoding, the next code cannot be decoded before the previous code is decoded. The above steps solve the problem of low decoding speed due to only serial decoding in the JPEG decoding process in related technologies, thereby simplifying the circuit structure , Save FPGA resources, improve the effect of decoding speed.
[0032] The above step S106 involves buffering the multiple-channel decoded data stream. In an optional embodiment, the multiple-channel decoded data stream is buffered into multiple first-in-first-out FIFO memories, thereby completing the multiple-channel decoding. Cache processing of the subsequent data stream.
[0033] The process of encoding multiple compressed data streams may involve encoding multiple compressed data streams in multiple ways. In an optional embodiment, after the first encoding method is performed on the multiple compressed data streams, When the second encoding method is used for encoding, the inverse encoding method corresponding to the second encoding method is used to inversely encode the multi-channel decoded data to obtain an inverse encoding result, and the inverse encoding result is buffered in the FIFO memory.
[0034] After de-encoding the multi-channel compressed data stream, in an optional embodiment, the inverse-encoding result is sequentially subjected to inverse quantization processing, inverse discrete cosine transform DCT processing, and color space conversion processing, thereby completing the multi-channel compressed data stream The final decoding.
[0035] In an optional embodiment, the first coding mode is Huffman coding, and the second coding mode is Z-word coding and run length coding.
[0036] In an alternative embodiment, the compressed data stream is a compressed data stream of a JPEG file.
[0037] In this embodiment, a data stream decoding device is also provided, which is used to implement the above-mentioned embodiments and preferred implementations, and those that have been described will not be repeated. As used below, the term "module" may implement a combination of software and/or hardware with predetermined functions. Although the devices described in the following embodiments are preferably implemented by software, hardware or a combination of software and hardware is also possible and conceived.
[0038] image 3 It is a structural block diagram of a data stream decoding device according to an embodiment of the present invention, such as image 3 As shown, the device includes: a receiving module 32 for receiving multiple compressed data streams, where the compressed data stream is a data stream using a first encoding method, and the first encoding method needs to be decoded in a serial decoding method; The first decoding module 34 is configured to use multiple decoders to respectively decode the multiple compressed data streams in parallel to obtain multiple decoded data streams; the buffer module 36 is configured to buffer the multiple decoded data streams ; The second decoding module 38 is used to perform subsequent decoding processing on the buffered multi-channel decoded data stream in a polling manner.
[0039] Further, the buffer module 36 is also used to buffer the multiple-channel decoded data streams into multiple first-in first-out FIFO memories.
[0040] Further, the second decoding module 38 is further configured to use the inverse encoding method corresponding to the second encoding method to inversely encode the multi-channel decoded data when the second encoding method is also used for encoding the multi-channel compressed data stream. , Get the de-encoding result, and buffer the de-encoding result into the FIFO memory.
[0041] Further, the first coding mode is Huffman coding mode, and the second coding mode is Z-word coding and run length coding.
[0042] It should be noted that each of the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following way, but not limited to this: the above modules are all located in the same processor; or, the above modules are located separately The first processor, the second processor, and the third processor...
[0043] In view of the above-mentioned problems in the related art, the following describes with an optional embodiment, and the above-mentioned optional embodiment and its optional implementation manner are combined in this optional embodiment.
[0044] This optional embodiment provides a device for parallel batch processing of JPEG decoding using FPGA. Compared with the traditional JPEG decoding device, the decoding speed is doubled on the premise that the device complexity is slightly increased.
[0045] The FPGA parallel batch processing JPEG picture decoding device of this optional embodiment is composed of the following parts: multiple parallel huffman decoders, multiple first input first output (FIFO) buffers, and 1 reverse Z-code encoding And an inverse run encoder, an inverse quantizer, an inverse (DiscreteCosineTransform, referred to as DCT) converter and a color space converter.
[0046] The implementation scheme of this optional embodiment includes the following steps:
[0047] The first step: Multiple huffman decoders (6 to 8) receive the compressed data streams of multiple JPEG files independently, and independently perform huffman decoding. The decoding result is placed in the corresponding FIFO of each channel.
[0048] Step 2: Reverse z-word encoding and reverse run-length encoder poll the multi-channel FIFO from top to bottom, read the polled first non-empty FIFO data for reverse z-word and reverse run decoding and put the result into In the next FIFO.
[0049] The third step: the inverse quantizer reads the data of the upper FIFO and searches the corresponding quantization table according to the channel number in the data for inverse quantization.
[0050] Step 4: Perform inverse DCT transformation on the inverse quantization result.
[0051] Step 5: Send the result of the inverse DCT transformation to the color converter for color space conversion, and finally output each channel of red, green and blue (RedGreenBlue,) RGB data.
[0052] The focus of this optional embodiment lies in the multiplexing structure of the multi-channel parallel huffman decoder designed in this device.
[0053] Explanation of terms in the undergraduate selected examples:
[0054] FPGA: Field Programmable Gate Array. It has the characteristics of flexible architecture and logic unit, high integration, and wide application range. It can be used to implement larger-scale circuits with flexible and convenient programming. At present, the main manufacturers include xilinx, altera, lattice, etc. Inside FPGA, logic function blocks are arranged in an array, and these logic function blocks are connected by programmable interconnect resources.
[0055] Huffman decoder: Huffman coding (Huffman Coding) is an encoding method that can effectively and losslessly compress data. It is widely used in file, image and video compression. Huffman decoding is the reverse process of encoding.
[0056] Reverse Z-word and reverse run length encoder: Both Z-word encoding and run-length encoding are also encoding methods, which are very helpful for image data compression. Reverse Z-word encoding and reverse run-length encoding are their inverse processes and are used in decoding.
[0057] Inverse quantizer: Inverse quantization is the inverse process of quantization. The image needs to be quantized in the compression coding process to ignore details that are not sensitive to the human eye and reduce the amount of data.
[0058] Inverse DCT converter: the inverse process of DCT transformation. DCT transformation is cosine transformation. During the image compression process, the time domain signal is converted into frequency domain signal through cosine transformation. Because the physiological characteristics of the human eye are not sensitive to high frequency signals, so The high frequency signal in the frequency domain can be ignored to achieve the purpose of compressing the amount of data.
[0059] Color space converter: The general picture is in RGB (i.e. red, green and blue) format. This format is not suitable for compression. It needs to be converted to YUV (i.e. TV video or computer monitor video) format to be suitable for compression.
[0060] Figure 4 It is a block diagram of multi-channel compressed data stream processing structure in related technology, such as Figure 4 As shown, the multiple JPEG picture code streams respectively pass through respective huffman decoder, inverse z-word reverse run encoder, inverse quantizer, inverse DCT converter and color space converter to complete the decoding output. This design structure does not make full use of the asymmetry of the processing speed between the huffman decoder module and other modules. For each channel, an inverse z-word inverse run encoder, inverse quantizer, inverse DCT converter and color space conversion are designed separately. As a result, the entire circuit is extremely complex and consumes a lot of resources, directly affecting the layout and working frequency of the circuit, and limited by FPGA resources, the number of parallel channels is unlikely to be many.
[0061] This optional embodiment takes full advantage of the asymmetry that the huffman decoding speed is slow and the processing speed of other modules is fast, and all parts except the huffman decoding module are designed into a multiplex structure. Multiple huffman decoders in the device perform huffman decoding independently, and the decoding results are placed in each channel's respective FIFO. The subsequent reverse Z-word encoder and reverse run encoder poll each FIFO, and use the "first come first serve" strategy to process the data in each FIFO. Then, after FIFO buffering, inverse quantizer inverse quantization, inverse DCT transformation and color space converter conversion, finally output the decoded RGB data of each picture. compared to Figure 4 The circuit structure is simplified on a large scale.
[0062] Figure 5 It is a block diagram of a multi-channel compressed data stream processing structure according to an embodiment of the present invention, such as Figure 5 As shown, the connection relationship among multiple huffman encoders, FIFO buffers, inverse Z-word encoders, inverse run encoders, inverse quantizers, inverse DCT converters and color space converters in this design is described. 8 JPEG pictures are input to the device at the same time, and the 8 huffman decoders in the device independently perform huffman decoding. The decoding speed of 8 channels is unequal and unpredictable. The result of huffman decoding is placed in each channel's respective FIFO. The subsequent reverse Z-word encoder and reverse run encoder poll each FIFO, and use the "first come first serve" strategy to process the data in each FIFO. Then, after FIFO buffering, inverse quantizer inverse quantization, inverse DCT transformation and color space converter conversion, finally output the decoded RGB data of each picture.
[0063] To sum up, the present invention eliminates the speed bottleneck, improves the overall decoding speed, and greatly accelerates the decoding speed of batch JPEG pictures by adopting a multiplexed parallel processing method for the serial links in the JPEG decoding process. Compared with the common multi-channel processing structure, the design of the present invention greatly simplifies the circuit structure by fully reusing some unit modules, saves FPGA resources, and can achieve the effect of increasing the operating frequency at the same time.
[0064] In another embodiment, a software is also provided, and the software is used to execute the technical solutions described in the above embodiments and preferred implementations.
[0065] In another embodiment, a storage medium is also provided. The storage medium stores the above-mentioned software. The storage medium includes, but is not limited to, an optical disk, a floppy disk, a hard disk, and an erasable memory.
[0066] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Above, alternatively, they can be implemented with program codes executable by the computing device, so that they can be stored in the storage device for execution by the computing device, and in some cases, can be executed in a different order than here. Perform the steps shown or described, or fabricate them into individual integrated circuit modules separately, or fabricate multiple modules or steps of them into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.
[0067] The above descriptions are only preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc., made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
