Method and apparatus for controlled recovery of error messages between independently operable processors
An independent operation, error information technology, applied in the direction of response error generation, error detection/correction, electrical digital data processing, etc., can solve the problems of debug information corruption, indeterminate debug information collection, etc.
Active Publication Date: 2019-01-15
APPLE INC
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In these worst cases, even though useful debug information may have been collected, the designer cannot be sure whether the debug information was collected before, during, or after the failure; in some cases, the debug information may even have been corrupted ,and many more
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[0035] Referring now to the drawings, wherein like numerals refer to like parts.
[0036] Detailed Description of Exemplary Embodiments
[0037] Exemplary embodiments of the present disclosure will now be described in detail. While these implementations are primarily discussed in the context of the Peripheral Component Interconnect Express (PCIe) standard (e.g., as described in "PCI Express Base Specification Revision 3.1," published October 8, 2014), those of ordinary skill will recognize The present disclosure is not limited thereto. In fact, aspects of the present disclosure may be used with any device or network of devices configured to incorporate and coordinate multiple independent processing elements as disclosed herein.
[0038] While the following embodiments describe specific implementations such as error messages, communication protocols between independently operable processors, and a consistent framework for error message recovery within the range of potentially...
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The present disclosure relates to methods and apparatus for controlled recovery of error messages between independently operable processors. Methods and apparatus for controlled recovery of error messages between two or more independently operable processors are disclosed. The present disclosure provides solutions for saving error information in case of fatal errors, coordinating reset conditions among independently operable processors, and implementing a consistent framework for error information recovery across potentially fatal errors. In one exemplary embodiment, the application processor AP and baseband processor BB implement abort handler and power down handler sequences that enable error recovery in a wide range of crash scenarios. In a variant, the assertion of the signal between the AP and the BB causes the AP to reset the BB only after the error recovery procedure has been successfully completed.
Description
technical field [0001] The present disclosure relates generally to the field of consumer electronic devices and their networking. More specifically, in one exemplary aspect, the present disclosure relates to methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. Aspects of the present disclosure relate, for example, to preserving error information in the event of a fatal error, coordinating reset conditions between independently operable processors, and consistent methods for performing error information recovery over a range of potentially fatal errors. frame. Background technique [0002] Historically, most computing devices have been designed according to the personal computer (PC) paradigm, in which a single processor is primarily responsible for managing software execution. However, computing devices have evolved significantly to accommodate a diverse ecosystem of designs and uses; moreover, processo...
Claims
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IPC IPC(8): G06F11/07
CPCG06F11/0712G06F11/0715G06F11/0757G06F13/4022G06F13/4221G06F11/0778G06F11/2028G06F2201/805G06F11/14
Inventor K·桑吉S·加格V·派科夫张海宁
Owner APPLE INC