Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor integrated circuit, latch circuit and flip-flop

A technology of integrated circuits and latch circuits, applied in logic circuits, electrical components, and generating electric pulses, etc., can solve the problems of reduced transistor drive capability, inability to maintain latch signals, and inability to write data signals, etc., to achieve low power consumption volume effect

Active Publication Date: 2019-01-11
PANASONIC SEMICON SOLUTIONS CO LTD
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, in the conventional technologies described in Patent Documents 1 and 2, the power supply voltage has decreased due to the reduction in power consumption of semiconductor integrated circuits in recent years, or the size of transistors has also decreased in accordance with the demand for smaller areas. The drive capability of the transistor for writing the data signal is reduced. If the drive capability of the transistor is lower than that of the inverter that generates the latch feedback signal, the data signal cannot be written.
In addition, if the driving capability of the inverter is reduced as much as possible, the latch signal cannot be maintained.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor integrated circuit, latch circuit and flip-flop
  • Semiconductor integrated circuit, latch circuit and flip-flop
  • Semiconductor integrated circuit, latch circuit and flip-flop

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0032] Figure 1A An example of a circuit diagram of the latch circuit according to Embodiment 1 is shown. Figure 1B It is a conceptual diagram showing a circuit for processing a clock signal in the latch circuit according to the first embodiment.

[0033] like Figure 1A As shown, the latch circuit 100 has: two inverters 110 (first inverter) and an inverter 130 (second inverter) connected in series between the input terminal IN and the output terminal OUT; The control switch 120 between the inverter 110 and the inverter 130; and the latch feedback section 140 (semiconductor integrated circuit), which receives the latch signal Q1 output from the output terminal OUT to generate the latch feedback signal B, and Feedback to the input of inverter 130 . Between the output of the inverter 110 and the input of the control switch 120, the node N10 is connected, between the output of the control switch 120, the input of the inverter 130, and the output of the latch feedback part 140,...

Embodiment approach 2

[0046] Figure 2A An example of a circuit diagram of a latch circuit according to Embodiment 2 is shown. exist Figure 2A In addition to the latch feedback section 140, the configuration and Figure 1A same or similar. Figure 2B is a conceptual diagram of a circuit for processing a clock signal in the latch circuit according to Embodiment 2, and shows Figure 1B same circuit.

[0047] like Figure 2A As shown, the latch feedback unit 140 includes: an N-type transistor T5 (the fourth transistor) whose gate and drain are connected to the power supply; a P-type transistor T4 (the first transistor) whose source is connected to the power supply and whose gate is connected to the node N12. ); a P-type transistor T1 (fifth transistor) connected between the node N13 to which the drain of the P-type transistor T4 is connected and the node N11, and whose gate is connected to the source of the N-type transistor T5 via the node N15; N-type transistor T2 (second transistor) whose dra...

Embodiment approach 3

[0055] Figure 3A An example of a circuit diagram of a latch circuit according to Embodiment 3 is shown. exist Figure 3A In, the configuration other than the latch feedback section 140 is the same as Figure 1A same or similar. and, if Figure 3A As shown, the latch feedback section 140 and the Figure 2A Compared with the structure of the above, the connection between the gate of the N-type transistor T2 (second transistor) and the source of the N-type transistor T5 (sixth transistor) is omitted, and a P-type transistor T6 (fourth transistor) is also provided, the gate of which is The electrode and the drain are grounded, and the source is connected to the gate of the N-type transistor T2. Figure 3B is a conceptual diagram of a circuit for processing a clock signal in the latch circuit according to Embodiment 3, and shows Figure 1B same circuit.

[0056] By this composition, with Figure 1A Similarly, the latch function is realized by the latch feedback unit 140 and ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

Description

technical field [0001] This application relates to a semiconductor integrated circuit, and a latch circuit and a flip-flop including the semiconductor integrated circuit. Background technique [0002] Many latch circuits as well as flip-flops are used in semiconductor integrated circuits. With the popularization of mobile devices, the demand for low power consumption of semiconductor integrated circuits is increasing. Therefore, low power consumption is also desired for latch circuits and flip-flops. [0003] In general, in order to reduce the power consumption of the latch circuit and the flip-flop, it is desirable to reduce the number of transistors present on the transmission path of the clock signal as much as possible. For example, when the data signal is written into the latch circuit, a mechanism that temporarily disconnects the latch feedback signal according to the clock signal is used to facilitate writing, and since the control switch as the disconnecting mechani...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/356H03K3/037H03K19/0948
CPCH03K3/012H03K3/037H03K3/356026H03K3/35606H03K3/356121
Inventor 中西和幸
Owner PANASONIC SEMICON SOLUTIONS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com