d flip flop
A flip-flop, MOS tube technology, applied in pulse technology, pulse generation, electrical components, etc., can solve problems such as DICE structural reinforcement failure, improve reliability and safety, avoid simultaneous flipping, and inhibit diffusion effects.
Active Publication Date: 2019-01-22
HUNAN RONGCHUANG MICROELECTRONICS CO LTD
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Problems solved by technology
However, if the distance between the sensitive node pair is too small, the charge generated after the single particle bombards the sensitive node will easily diffuse into its sensitive node, causing a pair of sensitive nodes in the DICE structure to flip at the same time, resulting in multi-node flipping of the circuit. DICE structural reinforcement failure
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[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.
[0021] It should be noted that like numerals and let...
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The invention provides a D flip-flop, and relates to the field of flip-flop. The D flip-flop comprises at least a pair of MOS tubes of same conduction type, each MOS tube comprises a first substrate or a first trap of which the conduction type is opposite to the MOS tube, the first substrate of one MOS tube in each pair of MOS tubes of same conduction type is provided with a second trap having the same conduction type with the MOS tube or the first trap of one MOS tube in each pair of MOS tubes of same conduction type is provided with a second substrate having the same conduction type with the MOS tube, and the second substrate or the second trap is positioned between the two MOS tubes of each pair of MOS tubes. When the sensitive node of the D flip-flop is hit, electric charges generated when the sensitive node is bombarded can be restrained from diffusing at the adjacent sensitive node, the simultaneous overturn of the plurality of sensitive nodes can be effectively avoided, and the reliability and security of the D flip-flop can be improved.
Description
technical field [0001] The present invention relates to the field of flip-flops, in particular to a D flip-flop. Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event flip. The higher the linear energy transfer (LET) value of the single particle bombarding the integrated circuit, the stronger the electron pulse generated. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, it is particularly important to develop advanced anti-single event upset hardening technolog...
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IPC IPC(8): H03K3/353
CPCH03K3/353
Inventor 杨国庆朱定飞王建军徐庆光
Owner HUNAN RONGCHUANG MICROELECTRONICS CO LTD