A method for controlling the write operation of SRAM with ultra-low write power consumption

Abstract

The invention relates to a static random access memory with ultralow writing power consumption and a control method of writing operation of the static random access memory. A traditional 6-tube storage unit is changed into a PMOS (P-channel Metal Oxide Semiconductor) tube from an NMOS (N-channel Metal Oxide Semiconductor) transistor and a ground end connected with a previous NMOS pulling-down tube source end is changed into a dummy ground end of an NMOS current source controlled by a writing line opposite WWL_N; the traditional 6-tube storage unit is modified into a voltage type sensitive amplifier; the sensitive amplifier is added into a writing data channel to be used as writing data cache. When writing operation is carried out, the writing data is written to the sensitive amplifier firstly and stored; an amplification line and an alignment line of the sensitive amplifier are discharged and the self amplification capability of the storage unit is utilized; the writing operation of the storage unit can be finished by only very small bit line voltage difference so that bit line overturning power consumption consumed by the writing operation is saved. Compared with traditional bit line full-swing writing operation, the bit line overturning power consumption consumed by single time of the writing operation is reduced by 4.2 times.

Description

technical field [0001] The invention relates to the field of static random access memory design, in particular to a static random access memory with ultra-low write power consumption. Background technique [0002] As an important storage element in integrated circuits, SRAM is widely used in high-performance computer systems (CPU), system-on-chip (SOC), handheld devices, etc. due to its high performance, high reliability, and low power consumption. computing field. According to the estimate of ITRS, the international semiconductor technology blueprint, by 2016, the area of ​​embedded SRAM will account for 90% of the area of ​​the entire computer system (CPU) and system on chip (SOC). The power consumed by it accounts for 40% of the whole computer system (CPU) on chip, system on chip (SOC), and dynamic power consumption accounts for about 14%. For the write operation of SRAM, usually the bit line needs full swing operation. Compared with the read operation, the bit line onl...

AI Technical Summary

Problems solved by technology

For the write operation of SRAM, usually the bit line needs full swing operation. Compared with the read operation, the bit line only needs to discharge a small voltage difference, and the small voltage difference of the sense amplifier is amplified to the full swing. Consumes more power

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