A Two-port SRAM with Low Write Power Consumption

Abstract

The invention provides a two-port static random access memory with low write power consumption. The write prediction comparator compares the write data in the previous cycle with the current write data. If they are different, the write bit line equalization signal is set to valid, otherwise it is invalid. ; When there are continuous write "0" or write "1" operations, because the data held on the bit line is the same as the data to be written, the write pre-judgment comparator will invalidate the write bit line equalization signal, so the bit line No reversal occurs; when the data written twice in a row is different, the write pre-judgment comparator sets the write bit line equalization signal to be valid, and the charges on the write bit line and the write bit line are redistributed, and the write bit line and the write bit line are reversed. Equalize to the middle level, then the write bit line equalization signal is invalid, the write enable is valid, and the write driver will drive the bit line and the bit line back to a new level. Compared with the traditional two-port SRAM based on the write bit line equalization technology, the invention reduces the power consumption of the write bit line flip by 50% when the write data flip rate is 50%.

Description

【Technical field】 [0001] The invention relates to the field of static random access memory, in particular to a two-port static random access memory with low write power consumption. 【Background technique】 [0002] According to the forecast of the International Semiconductor Technology Roadmap (ITRS), the area of ​​the SRAM will become larger and larger, and by 2015, it will account for more than 94% of the area of ​​the entire system-on-chip (SOC). Therefore, the power consumption of the SRAM will directly affect the power consumption of the entire SOC. [0003] see figure 1 as shown, figure 1 It is a two-port SRAM data path using write bit line equalization technology. The typical data path includes bit line precharge and equalization circuits, memory cells, and write drivers. [0004] The pre-charging and equalizing circuit is composed of PMOS transistor 105 . The storage unit is composed of a pair of cross-coupled inverters 101 , 104 and NMOS transmission transistors...

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Problems solved by technology

Therefore, the power consumption of the SRAM will directly affect the power consumption of the entire SOC

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