Two-port static random access memory with low writing power consumption

Abstract

The invention provides a two-port static random access memory with low writing power consumption. A writing prediction comparator compares previous-cycle writing data with current writing data; if the data are different, a writing bit line balance signal is set as a valid signal, and otherwise, the signal is set as an invalid signal; when continuous 0-writing operation or 1-writing operation occurs, because data retained on a bit line are the same as data needing to be written, the writing prediction comparator sets the writing bit line balance signal as the invalid signal, so that the bit line is not turned over; when the data written for successive two times are different, the writing prediction comparator sets the writing bit line balance signal as the valid signal, charges on the writing bit line and a writing bit line back are reallocated, and the writing bit line and the writing bit line back are balanced to an intermediate level; then the writing bit line balance signal is invalid, a writing enable signal is valid, and a writing driver drives the writing bit line and the writing bit line back to a new level. Compared with a conventional two-port static random access memory based on a writing bit line balancing technology, the two-port static random access memory with the low writing power consumption has the advantages that when the turnover rate of the writing data is 50 percent, the turnover power consumption of the writing bit line is reduced by 50 percent.

Description

【Technical field】 [0001] The invention relates to the field of static random access memory, in particular to a two-port static random access memory with low write power consumption. 【Background technique】 [0002] According to the forecast of the International Semiconductor Technology Roadmap (ITRS), the area of ​​SRAM will become larger and larger, and by 2015, it will account for more than 94% of the entire system-on-chip (SOC) area. Therefore, the power consumption of the SRAM will directly affect the power consumption of the entire SOC. [0003] see figure 1 as shown, figure 1 It is a two-port SRAM data path using write bit line equalization technology. The typical data path includes bit line precharge and equalization circuits, memory cells, and write drivers. [0004] The pre-charging and equalizing circuit is composed of PMOS transistor 105 . The storage unit is composed of a pair of cross-coupled inverters 101 , 104 and NMOS transmission transistors 102 , 103 . ...

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Problems solved by technology

Therefore, the power consumption of the SRAM will directly affect the power consumption of the entire SOC

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