A Static Random Access Memory Using Static Write Technology to Reduce Write Power Consumption

Abstract

The invention provides a static random access memory for reducing writing power consumption by adopting a static writing technology. A bit line pre-charging signal generating circuit is used for detecting whether writing enabling is valid or not on the rising edge of a clock, and if a writing enabling signal is valid, a bit line pre-charging signal is invalid; otherwise, the bit line pre-charging signal is valid, namely, the bit line pre-charging signal is invalid during writing operation. A static writing driver consists of a phase inverter and a three-state gate; when writing enabling is valid, the output of the static writing driver is used for driving a bit line directly. Compared with the conventional static random access memory, the static random access memory has the advantages that pre-charging operation on the bit line is not needed during writing operation. When continuous '0' or '1' writing operation occurs, data kept on the bit line are the same as data needing to be written, so that the bit line is not flipped, thereby saving the power consumption. Under the condition that the flipping probability of written data is a half, the flipping power consumption of a writing bit line is lowered by 50 percent in comparison to the conventional design.

Description

【Technical Field】 [0001] The invention relates to the field of static random access memory design, in particular to a static random access memory that adopts static writing technology to reduce writing power consumption. 【Background technique】 [0002] According to the International Semiconductor Technology Blueprint (ITRS) forecast, the area of ​​SRAM will become larger and larger, and by 2014, it will account for more than 94% of the entire system-on-chip (SOC) area. Therefore, the power consumption of the SRAM will directly affect the power consumption of the entire SOC. [0003] See figure 1 As shown, figure 1 Write the data path schematic diagram for a typical SRAM. This typical data path includes bit line precharge and equalization circuits, memory cells and write drivers. [0004] The bit line precharge and equalization circuit is composed of PMOS transistors 101-103. The storage unit is composed of a pair of cross-coupled inverters 105 and 107 and NMOS transmission tubes 1...

AI Technical Summary

Problems solved by technology

When there are continuous "0" or "1" in the write data, that is, when the value held on the bit line 115 and the bit line 118 is the same as the value of the write bit line 120 and the write bit line 121, the precharge operation and discharge operation implies additional energy loss

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