Logic Analyzer for Detecting Stalls

Abstract

A microprocessor includes a cache including a tag array, a tag pipe that arbitrates access to the tag array, and a logic analyzer for investigating starvation, livelock, or deadlock conditions. A logic analyzer including read logic coupled to the tag tube is configured to record snapshots of transfers accessing the tag array.

Description

technical field [0001] The present invention relates to hang detection logic, and more particularly, to hang detection logic for last-level caching. Background technique [0002] The tag pipeline of the last level cache (LLC) provides the means to access tag, MESI and LRU arrays. A tag pipeline (also referred to herein as a tag pipe) prioritizes requests and makes decisions on how to respond to certain requests. For example load requests from lower level caches such as L1D will cause queue entries to be pushed for the purpose of tracking state. Data load queue entries then arbitrate ownership of the tag pipeline. Once it is granted ownership of the tag pipeline, the queue entry accesses the tag MESI queue array to see if its address is in the queue array. If it is, then at the end of the pipeline, the queue entry decides whether to hit or miss or need to snoop other caches based on whether the address is in the cache and based on which other cache has the line. [0003] ...

AI Technical Summary

Problems solved by technology

A halt occurs when thread 0 owns the resource and its task ends, but prevents threads 1 and 2 from attempting to free the resource with repeated read-modify-write 0

These kinds of deficient states are an unplanned feature of the architecture that prioritizes loads relative to other loads, and are difficult to predict

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