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Wafer thinning method

A wafer and ring-shaped technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as low production efficiency, easy warpage and deformation, and fragile wafers, and achieves a wide tolerance range, The effect of ensuring efficiency, reducing process difficulty and complexity

Active Publication Date: 2016-10-05
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, when the wafer is thinned below a certain thickness, the wafer becomes extremely brittle, such as warping, deforming or even chipping
However, in order to avoid wafer cracking and deformation as far as possible in the existing technology, many restrictions are imposed on various processes during wafer production and bonding, which will lead to lower overall production efficiency.

Method used

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Embodiment Construction

[0045] In order to reduce cracks or warping of the wafer when the wafer is thinned, in the prior art, the wafer to be thinned is adhered to a pad wafer by glue in advance before the wafer is thinned, and then A thinning process is performed on the tape thinned wafer attached to the pad wafer. The thinned wafer is then removed from the backing wafer for use. However, this method has a small range of temperature tolerance, especially high temperature, because the glue may start to decompose or soften at a slightly higher temperature (higher than 100 degrees Celsius), which will lead to thinned wafers and The gasket wafers cannot be tightly fixed, which may cause cracks or warping of the wafer to be thinned during the thinning process.

[0046] At the same time, in order not to make the temperature too high in the prior art, the ambient temperature of the wafer has to be kept within a certain temperature. But this will affect the progress of other processes, bring troubles to t...

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PUM

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Abstract

The present invention provides a wafer thinning method, comprising: providing a first wafer to be thinned, the first wafer includes a front surface for forming a semiconductor device and a back surface opposite to the front surface; forming a first inorganic material layer on the front side of a wafer; providing a second wafer for supporting the first wafer, the second wafer including a working surface for cooperating with the front side of the first wafer; forming a second inorganic material layer on the working surface of the second wafer; bonding the first inorganic material layer to the second inorganic material layer to bond the first wafer to the second wafer Bonding; removing part of the material on the back of the first wafer to reduce the thickness of the first wafer; debonding the thinned first wafer from the second wafer. The beneficial effect of the present invention is that: the ambient temperature tolerance range is wider, which is beneficial to reduce the difficulty and complexity of other subsequent processes, and thus is beneficial to ensure the efficiency of the entire process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a wafer thinning method. Background technique [0002] Packaging technology is essentially a chip packaging technology. This packaging is necessary for the chip because the chip must be isolated from the outside world to prevent impurities in the air from corroding the chip circuit and causing electrical performance degradation. On the other hand, packaged chips are also easier to install and transport. The quality of the packaging technology directly affects the performance of the chip itself and the design and manufacture of the printed circuit board connected to it. [0003] The current packaging technology has gradually transitioned from surface mount technology and ball grid array terminal packaging technology (BallGrid Array, BGA) to three-dimensional packaging technology (3D Package). Three-dimensional packaging technology can be divided into three-dimensional ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/304
Inventor 施林波陈福成刘尧
Owner SEMICON MFG INT (SHANGHAI) CORP
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