Pad thickness monitoring method and wafer with pad thickness monitoring structure
A thickness monitoring and pad technology, which is used in semiconductor/solid-state device testing/measurement, semiconductor/solid-state device components, semiconductor devices, etc., to prevent a large number of products from being scrapped and improve yield
Active Publication Date: 2019-03-15
CSMC TECH FAB2 CO LTD
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Problems solved by technology
[0003] In order to solve the problem in the prior art that there is no effective method for monitoring the thickness of the pad, the present invention provides a method for monitoring the thickness of the pad
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[0023] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0024] figure 2 It is a flowchart of a pad thickness monitoring method in an embodiment, including the following steps,
[0025] S110, providing a semiconductor substrate located in a wafer testing area.
[0026] In the process of semiconductor preparation, in order to perform some performance tests on the prepared semiconductor devices, some areas on the wafer (wafer) other than the semiconductor device area are often divided as test areas, so that the wafer includes semiconductor devices. Device area and test area. In this embodiment, the pad thickness monitoring structure (testkey) for reali...
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Abstract
The present invention discloses a boding pad thickness monitoring method. The method comprises the following steps: providing a semiconductor substrate located in a wafer test area; forming an intermetallic dielectric layer on the semiconductor substrate; performing etching of the intermetallic dielectric layer and filling the intermetallic dielectric layer with first metal to form a first metal area; forming a second layer through deposition between the intermetallic dielectric layer and the surface of the first metal area, wherein the loss of the first metal in the etching technology is smaller than the loss of the second metal; etching at least part of the second metal layer at the surface of the first metal area; forming interlayer dielectric layers among the surface of the first metal layer, the surface of the second metal layer and the surface of the intermetallic dielectric layer through deposition; etching at least part of the interlayer dielectric layers at the surface of the second metal layer and the surface of the first metal area; and measuring the height difference between the upper surface of the second metal layer and the upper surface of the first metal area to obtain the thickness of the bonding pad. The bonding pad thickness monitoring method can realize the effective monitoring of the thickness of the bonding pad. The present invention further discloses a wafer with a bonding pad thickness monitoring structure.
Description
technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a pad thickness detection method and a wafer with a pad thickness monitoring structure. Background technique [0002] In the final stage of chip preparation, it is necessary to define some pads on the chip for connecting leads, testing electrical performance and yield, etc. The area used to connect the leads needs to have good conductivity, so the material is usually aluminum, so it is also called an aluminum pad (AL pad). It is surrounded by media to play the role of isolation and protection. In the process preparation sequence, the metal (such as aluminum) used to form the pad is deposited first, then the dielectric is deposited, and finally the dielectric on the metal surface is etched away so that the metal is exposed to form the pad. Due to process fluctuations, too thin top metal deposition or too much metal loss (loss) during etching, the final remainin...
Claims
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IPC IPC(8): H01L21/66H01L23/544
Inventor 李健胡骏
Owner CSMC TECH FAB2 CO LTD