memory array

Abstract

The invention discloses a memory array. The memory array comprises a plurality of two-tube memory units, a plurality of mutually paralleling bit lines, and a plurality of mutual-insulation word lines vertical to the bit lines, two memory tubes which are adjacent up and down of the whole memory array share a source end or a leakage end in a back-to-back manner, a row of left and right adjacent memory tubes share a grid electrode, the grid electrodes of the memory tubes are connected with the memory tube word lines, the whole memory array shares a P trap, the bit lines in a longitudinal same column direction are connected, and different columns of the bit lines of the memory units are respectively externally connected; the word lines in a transverse same row are connected, memory word lines are respectively externally connected, all selection tube word lines in all odd number rows are connected, and all selection tube word lines in all even number lines are connected; and all source ends are connected in a back-to-back manner, and all transverse source lines are respectively externally connected. The memory array can reduce electric leakage of unselected rows in the read operation, and can accelerate the reading speed.

Description

technical field [0001] The invention relates to the field of semiconductor device design, in particular to a memory array. Background technique [0002] figure 1 is a state-of-the-art memory array. This memory array includes a plurality of memory cells, each memory cell is composed of two tubes of memory (the selection tube and the storage tube are connected in series), and also includes a plurality of bit lines (BL) parallel to each other, perpendicular to the bit line and mutually connected to the bit line. insulated multiple word lines. Wherein, the direction parallel to the bit line (the direction in which the storage transistor and the selection transistor are connected in series) is defined as the vertical direction, and the direction parallel to the word line is defined as the horizontal direction. BL (bitline, bit line) is connected from one end of the storage tube, and SL (sourceline, source line) is connected from one end of the selection tube; the two adjacent ...

AI Technical Summary

Problems solved by technology

As shown in the figure, the source and drain potentials of the non-selected rows in this technical solution are all 0, so the solution of pre-charging to 0.85V and then pulling down needs to discharge a large number of sources and drains of the non-selected rows, which will affect the reading speed

Images