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Multi-purpose data transmission network routing device and method, chip and router

A data transmission network and purpose technology, applied in the field of multi-purpose data transmission network routing devices, can solve the problems of prolonged average transmission delay, waste of network bandwidth, low cost performance, etc., to reduce redundant information transmission, improve network transmission efficiency, The effect of improving throughput

Active Publication Date: 2016-11-23
INST OF COMPUTING TECH CHINESE ACAD OF SCI +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] At present, the existing many-core structure usually uses the figure 1 As shown in the routing structure, this traditional routing structure does not do special processing for the same data at different addresses, and sends the same data separately when the processor checks multiple destination addresses, which makes there are a lot of redundancy in the network on chip The data transmission, the network bandwidth is wasted, and the probability of network congestion increases due to the increase in the number of data packets on the network, and the average transmission delay is prolonged. Using multiple sets of networks can relieve congestion, but this will increase the network cost-effective

Method used

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  • Multi-purpose data transmission network routing device and method, chip and router
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  • Multi-purpose data transmission network routing device and method, chip and router

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Embodiment Construction

[0025] The present invention aims at the characteristics of multi-purpose data transmission existing on the many-core structure, and proposes a multi-purpose data transmission network routing device, method, chip, and router. Packets with different addresses and the same data are merged, and the data packets are in the form of figure 2 As shown, it includes packet header 201 and data 202. The packet header contains multiple addresses 204-207, and each address contains a valid bit 203. During the transfer of data packets between routers, multiple addresses can be disassembled according to the relative positions of the routers. , gradually decompose according to the target address, and send it to each destination node. Different from the traditional router design and implementation, the routing structure of the present invention adds data packet unpacking logic between the routing input port and the input buffer. The specific method is as follows: image 3 As shown, the steps o...

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Abstract

The invention provides a multi-purpose data transmission network routing device and method, a chip and a router, and relates to the field of routing structure design of a network on chip under a multi-core or many-core structure. The method comprises the steps of receiving original data packets; combining the original data packets with different destination addresses and same data, thereby generating combined data packets; carrying out group division operation on the combined data packets, thereby generating one or more data packets; sending the data packets to message input queues corresponding to the destination addresses according to the destination addresses; and selecting corresponding output ports to output the data packets in the message input queues through arbitration operation.

Description

technical field [0001] The invention relates to the field of routing structure design of an on-chip network under a multi-core or many-core structure, in particular to a multi-purpose data transmission network routing device, method, chip, and router. Background technique [0002] At present, more and more scientific or big data-oriented processors adopt a large-scale processing core structure on the chip in order to tap the parallelism of specific applications. The network on chip undertakes the function of exchanging data between different cores or transmitting synchronous messages. However, the increase in the number of processing cores also brings new challenges to the design of the on-chip network. The actual performance of some applications or execution modes that are sensitive to transmission delays largely depends on the transmission efficiency of the on-chip network. In the core structure, the operands of the calculation are transmitted through the on-chip network, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/741H04L12/861H04L12/863H04L12/933H04L12/935H04L45/74H04L49/111
CPCH04L45/74H04L47/50H04L49/109H04L49/30H04L49/9057
Inventor 谭旭唐志敏叶笑春王达张浩
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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