Real-time flat-field correction method of area array camera based on FPGA

Abstract

The invention discloses an optimized area-array camera flat field correction real time algorithm implemented on the basis of an FPGA. The method is combined with the characteristics of FPGA parallel computation, and resource limitation in the FPGA is taken into consideration. The algorithm method based on blocks is adopted, blocking is conducted on a sensor array, the method is combined with the interpolation algorithm on the basis of blocking, resource consumption is reduced, and meanwhile each point is computed. The real time algorithm provides possibility for an area array camera to implement the real time FFC correction algorithm under high resolution and high frame rate, and provides high output image quality for high-resolution high-frame-rate application occasions. By using the optimized algorithm, real-time correction is successfully conducted on PRNU and the vignetting effect on the premise that the requirements for high resolution and high frame rate are met.

Description

technical field [0001] The invention relates to the technical field of image algorithms, in particular to an FPGA-based real-time flat-field correction method for an area array camera. Background technique [0002] In photoelectric imaging systems, especially in area array camera imaging systems, the image signal cannot fully reflect the actual target. The reasons mainly include two aspects: (1) The response inconsistency caused by the CCD or CMOS sensor manufacturing process (also known as PRNU ); (2) The vignetting effect caused by optical diffraction phenomena and various deviations of the optical system. In order to ensure the quality of the image output, it is generally necessary to correct the acquired original image with a flat-field correction (FFC) algorithm to make it meet the application requirements. Since PRNU and vignetting effects are often non-linear, in the FFC algorithm, correction is mainly performed by multiplication. The FFC algorithm can be summarized...

AI Technical Summary

Problems solved by technology

But for the high-resolution FFC algorithm, FPGA also has its own shortcomings, that is, the internal resources are limited, and it may not be able to cope with the storage resource requirements of high-resolution images.

For example, for KAI-47051, the number of pixels is 47.8MB, that is, based on the minimum 8-bit per pixel, 47.8MB of storage space is required to save the AI ​​array corresponding to an image; It is also difficult for FPGAs to meet this requirement

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