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Chip test structure and silicon chip

A chip testing and silicon wafer technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problem of inability to comprehensively detect the quality of chips on silicon wafers

Active Publication Date: 2016-12-07
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The problem to be solved by the present invention is: the quality of the chip on the silicon wafer cannot be fully detected according to the existing silicon wafer

Method used

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  • Chip test structure and silicon chip
  • Chip test structure and silicon chip
  • Chip test structure and silicon chip

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0045] Such as image 3 As shown, the present embodiment provides a silicon wafer 10, which includes several chips 11 separated by several dicing lines 12 arranged vertically and horizontally. The sealing ring 13 is disposed between the dicing line 12 and the chip 11 , and the sealing ring 13 surrounds the chip 11 . The sealing ring 13 can protect the chip 11 when the integrated circuit is manufactured on the silicon chip 10 and the integrated circuit is packaged. The silicon wafer 10 also includes a chip test structure 14 located between the sealing ring 13 and the chip 11 , that is, the chip test structure 14 is located at the periphery of the chip 11 . In a modified example of the present embodiment, the silicon wafer 10 may not have the sealing ring 13 .

[0046] Such as Figure 4 As shown, the chip test structure 14 includes a dielectric layer 141 on a substrate 140 and a conductive structure. The conductive structure includes: an active region 142 located on the surf...

no. 2 example

[0061] The difference between the second embodiment and the first embodiment is that in the second embodiment, as Figure 5 As shown, the number of the active region 142 is 1, and the number of the first metal lines 144, 146, 147, 148, 149 is 2, and the active region 142 connects the bottom two through the second metal plug 143 The first metal wire 144 is electrically connected, and the conductive structure in the chip test structure 14 is in a "V" shape.

no. 3 example

[0063] The difference between the third embodiment and the first embodiment is that in the third embodiment, if Figure 6 As shown, the conductive structure in the chip test structure 14 does not have an active region and a second metal plug, and each first metal line 149 on the topmost layer passes through each layer of first metal lines 144, 146, 147, 148, And the first metal plug 145 is connected in series.

[0064] Specifically, the number of first metal lines 144 in the bottommost layer is N, and N is equal to 2, the number of first metal lines 149 in the topmost layer is N+1 (that is, 3), and the number of first metal lines in other layers is 2N. (ie 4) pieces. Each bottom first metal line 144 electrically connects two adjacent first metal lines 146 on the second bottom layer through a first metal plug 145, and the two topmost first metal lines 149 at both ends of the chip test structure 14 pass through the first metal plug 145. A metal plug 145 is respectively electri...

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Abstract

A chip test structure and a silicon chip are provided wherein the chip test structure comprises a dielectric layer on a substrate and a conductive structure. The conductive structure includes a plurality of first metal lines located in the dielectric layer. The number of the first metal lines at each layer above the first metal line at the lowest layer is two and the first metal lines between neighboring layers are separated by the dielectric layer and the first metal lines at neighboring layers are separated by the dielectric layers. A first metal plug is provided in the dielectric layer between the first metal lines at neighboring layers and is electrically connected with the first metal lines at the neighboring layers. The first lines at the top layer are in series connection through the first metal lines at each layer under the top layer and the first metal plugs. According to the invention, it is possible to administrate comprehensive quality examination over a silicon chip.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip testing structure and a silicon chip. Background technique [0002] Such as figure 1 As shown, the existing silicon wafer 1 has a plurality of chips 2, and the plurality of chips 2 are separated by a plurality of cutting lines 3 arranged vertically and horizontally. 4 is located on the periphery of chip 2. [0003] Generally speaking, the production of integrated circuits is mainly divided into three stages: the manufacture of silicon wafers, the fabrication of integrated circuits, and the packaging of integrated circuits. When carrying out integrated circuit fabrication and integrated circuit packaging on the silicon wafer 1, the sealing ring 4 can protect the chip 2, for example: stop pollutants from diffusing to the chip 2, and when slicing (that is, cutting along the dicing road 3 When the chip 2 is cut from the silicon wafer 1 ), the stress crack transmitted...

Claims

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Application Information

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IPC IPC(8): H01L23/544
Inventor 郑利平隋振超唐建新
Owner SEMICON MFG INT (SHANGHAI) CORP
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