A high-performance DSP memory access pipeline circuit and its realization method

Abstract

The invention relates to a high performance DSP access streamline comprising the following elements: an access address calculation module used for forming a plurality of valid addresses according to access order forms; an access address conflict solving module used for determining storage access conflicts of the plurality of addresses and determining an address emission order; an access request sending module; an access request receive module; an inter-core access request sending module used for detecting an inter-core access request and sending same; a read access data retrieval module used for splicing data returned by a plurality of read addresses having conflicts after multi-cycle; a read access data output module used for outputting read access data. The method uses a streamline mode to realize read-write of a data SRAM; the streamline is short in depth and only at grade 5, i.e., single order execution needs 5 clock cycles; inter-core access order sending and receive modules can realize tight coupling of two DSP cores; the access address conflict solving method can realize the maximum data throughout efficiency.

Description

technical field [0001] The invention relates to the technical field of digital signal processors, in particular to a high-performance DSP memory access pipeline circuit and an implementation method thereof. Background technique [0002] One of the advantages of the digital signal processor DSP compared with the general-purpose central processing unit CPU is its powerful data computing capability. A large number of arithmetic and logic operation units or special processing units are integrated in the DSP core. In order to maximize these The parallelism of computing components requires the design of memory access channels that match the throughput. [0003] At present, mainstream DSPs use data cache instead of the memory access function. The working principle of data cache is the locality of program execution. If the locality of the running program is poor, it will cause frequent cache misses. Therefore, data cache cannot guarantee real-time processing requirements. At the sa...

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Problems solved by technology

[0003] At present, mainstream DSPs use data cache to replace the memory access function. The working principle of data cache is the locality of program operation. If the locality of the running program is poor, it will cause frequent cache misses. Therefore, it is difficult for data cache to guarantee real-time processing.

At the same time, a layered storage structure is often matched with the data cache. The data cache is located at the top of the layered storage structure. The built-in SRAM is generally small (K level), which is not conducive to multi-core shared data storage.

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