How Transistors Are Made
A manufacturing method and transistor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of conductive material residue, excessive removal of interlayer dielectric layer 13, etc., to avoid residue, improve yield rate, reduce The effect of manufacturing costs
Active Publication Date: 2020-05-08
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0008] However, the transistor formed in the prior art is prone to the problem that the interlayer dielectric layer 13 is excessively removed, causing conductive materials to remain on the surface of the interlayer dielectric layer 13
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Embodiment Construction
[0036] It can be seen from the background art that the manufacturing method of transistors in the prior art is prone to the problem of excessive etching of the interlayer dielectric layer. The reason for the excessive etching of the interlayer dielectric layer is analyzed in combination with the manufacturing process of the prior art transistor:
[0037] refer to Figure 1 to Figure 3 , in the process of manufacturing transistors in the prior art, in the process of removing the dummy gate 12 and removing the protective layer 14, residues are often formed on the surface of the interlayer dielectric layer 13. In order to improve the performance of the manufactured transistor, generally the dummy gate 12 and protective layer 14, before the step of filling the conductive material to form the gate 20, it is often used to contain CF 4 The post etch treatment (Post Etch Treatment, PET) is performed on the etched substrate with the gas. But since CF 4 The fluorine content in the sub...
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Abstract
A transistor manufacturing method comprises steps of forming a substrate, wherein pseudo grids and interlayer dielectric layers between the pseudo grids are formed in the substrate; removing the pseudo grids and forming grooves at the original position of the pseudo grids; after the grooves are formed, using cleaning gas to clean the substrate, wherein the cleaning gas comprises NF3; after the cleaning is completed, filling the grooves with conductive materials to form a grid. The invention adopts the cleaning gas including NF3 to clean the substrate after removing the pseudo grids and protection layers. Compared with common CF4 in the prior art, the NF3 cleaning gas has lower content of F, and thus the interlayer dielectric layers are effectively prevented from being over-etched in the pseudo grid removal process, residuals of the conductive materials on the surfaces of the interlayer dielectric layers are prevented, the yield of semiconductor devices is improved, and the device manufacturing cost is reduced.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a transistor. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. In order to reduce the parasitic capacitance of the gate of MOS transistors and improve the device speed, the gate structure of high-K gate dielectric layer and metal gate is adopted. Introduced into MOS transistors. [0003] The "Gate-Last" process is widely used in the manufacturing process of high-K gate dielectric layer and metal gate. Compared with the "Gate-First" process, the devices fabricated by the Gate-Last process can avoid the influence of the annealing of the source region or the drain region on other structures of the transistor. Therefore, the stability of devices fabricated by the gate-last process is higher. [0004] refer to Figure ...
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IPC IPC(8): H01L21/336H01L21/02
CPCH01L21/02071H01L29/66545
Inventor 黄瑞轩纪世良
Owner SEMICON MFG INT (SHANGHAI) CORP