GOA circuit control method

Abstract

The invention provides a GOA circuit control method. A plurality of GOA circuits is arranged on a liquid crystal panel; the liquid crystal panel is provided with a plurality of criss-cross gate electrodes and source electrodes. One or several gate electrodes correspond(s) to one GOA circuit, and in any frame picture and in an effectively vertical scanning period, the current level GOA circuit outputs the current level gate electrode output signal according to the input control signal and the gate electrode output signal generated by the previous level GOA circuit. At this time, the timing control chip of the LCD panel produces two output control signals at low levels. During the ineffectively vertical scan period, the input control signal of the current level GOA circuit remains low, the two output control signals are outputted alternately, and the GOA circuit is reset. The method of the invention can reduce the power consumption of a GOA circuit while ensuring the normal function of the GOA circuit, and does not cause the power leakage of pixels, a process leading to abnormal pictures.

Description

technical field [0001] The invention belongs to the field of liquid crystal display, in particular to a method for controlling a GOA circuit. Background technique [0002] The gate driver on array (GOA for short) technology is a technology for integrating a gate driver integrated circuit (Gate Driver Integrated Circuit) on an array (Array) substrate. The GOA circuit has multiple cascaded GOA units, and each GOA unit has a signal output terminal. The signal output terminal outputs a signal under the drive of the input signal, and the signal output from the signal output terminal is simultaneously used as the gate drive signal and the gate drive signal of the same row. The input signal of the next level GOA unit. [0003] The GOA circuit structure is as figure 1 As shown, under the control of GSP, CK and other input signals, the signal output terminal outputs Gout signal, and the Gout signal turns on the thin film transistor (TFT), and the source signal input screen is displ...

AI Technical Summary

Problems solved by technology

In the case of high temperature or unstable TFT retention performance, the voltage of the signal Q(n) generated in the GOA module during the invalid vertical scanning line (V-Blanking) will be pulled up, causing the gate voltage to fail to maintain the gate off voltage VGL causes pixel leakage, resulting in abnormal picture quality

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