Clock data recovery circuit

Abstract

The invention provides a clock data recovery circuit, and the circuit comprises a pulse detection circuit and a sampling circuit. The pulse detection circuit is used for carrying out the pulse detection and integration of a three-phase signal which is received by a receiving end and outputted by a mobile industry processor interface C-type physical layer protocol transmitting end, so as to recover a clock signal; The sampling circuit is used for carrying out the data sampling of the three-phase signal, which is received by the receiving end and outputted by the mobile industry processor interface C-type physical layer protocol transmitting end, based on pulse detection circuit recovery. The circuit carries out the pulse detection and integration of the three-phase signal, which is received by the receiving end and outputted by the mobile industry processor interface C-type physical layer protocol transmitting end, through employing the characteristics of the clock information in the three-phase signal, so as to recover the clock signal, thereby carrying out the sampling of the data through the recovered clock signal, and achieving the recovery of data. The whole circuit is simple in structure, and optimizes the recovered data and the jitter performance of a clock.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a clock data recovery circuit. Background technique [0002] With the continuous increase of people's needs and the number of various portable mobile devices, the amount of data transmission on communication links has increased exponentially, which requires a sharp increase in the speed and reliability of wired communication systems, especially data transmission. Therefore, as the core of data transmission equipment and facilities, high-speed serial communication technology needs to be greatly improved in speed, power consumption and reliability. As the most important part of the receiving end of high-speed serial communication, the clock data recovery circuit determines the quality of the clock at the receiving end of the entire system and the jitter and bit error rate of the recovered data. [0003] At present, there are many standard protocols for high-speed serial data...

AI Technical Summary

Problems solved by technology

Correspondingly, it is necessary to design a clock data recovery (CDR) circuit to recover clock and data. Since C-PHY uses three-phase signal technology to transmit data, the existing data clock recovery circuit still cannot meet the three-phase requirements. A clock data circuit that can realize the clock data recovery function of C-PHY has become a top priority

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