Method for manufacturing integrated chip
A manufacturing method and integrated chip technology, which are applied in the fields of logic circuit coupling/interface, instrument, and pulse technology using field effect transistors, can solve the problems of low adjustment efficiency of integrated chips, increase development cost, etc., and solve the problems of adjustment and repair. The effect of low efficiency, reduced development cost, and improved adjustment efficiency
Active Publication Date: 2017-02-15
SOI MICRO CO LTD
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[0006] An embodiment of the present invention provides a manufacturing method of an integrated chip, which is used to solve the technical problems of low efficiency of integrated chip repair and increased development cost in the prior art
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[0033] Please refer to figure 1 , the embodiment of the present application provides a method for manufacturing an integrated chip, which includes:
[0034] S101: Decompose the target device into N first small devices, each first small device is connected in series or in parallel with two MOS transistors, and N is an integer greater than 1;
[0035] S102: connect the target device in series or in parallel with M second small devices, each second small device is connected in series or in parallel with two MOS transistors, M is an integer greater than 1; the on-off of the two MOS transistors is used to control Whether to access the corresponding small device;
[0036] S103: Connect the output terminal of the decoder to the first gate of the two MOS transistors, the second gate of the two MOS transistors to the control port, and the output of the output terminal of the decoder The signal is used to control the on-off of the two MOS tubes;
[0037] S104: Control the output of t...
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The invention discloses a method for manufacturing an integrated chip. The method comprises the steps of: decomposing a target device into N first small devices; connecting the target device with M second small devices in series or in parallel; controlling whether the first small devices or the second small devices are connected by on and off of two MOS (Metal Oxide Semiconductor) transistors; connecting the output end of a decoder with first gates of the two MOS transistors, and connecting second gates of the two MOS transistors with a control port; controlling the output end of the decoder to output different level signals by applying different levels to the input port of the decoder, controlling on and off of the MOS transistors to control the connection of each first small device or each second small device to adjust the size of the target device, and determining the final size of the target device; and when the chip is packaged, fixing the potential of the port according to the magnitude of the port level corresponding to the final size. The technical solution solves the technical problems of low adjustment and repair efficiency and development cost increase of the integrated chip in the prior art.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method for manufacturing an integrated chip. Background technique [0002] In the process of testing the integrated circuit, if it is found that the integrated chip has a circuit function failure or The performance fails to meet the detailed specifications of the product and needs to be corrected. The specific correction methods include: [0003] 1. Determine and modify the size of the device (MOS tube, resistor, capacitor or inductor) by re-simulating the internal circuit to improve the function or performance of the circuit. But in this way, the layout of the integrated chip must be re-plate-made, and the verification and supply of the product can be realized through re-taping. Since the size of the modified device is determined through simulation, it cannot be directly verified by the chip, and the reliability is not high; in addition, it is necessary to re-pla...
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IPC IPC(8): G06F17/50H03K19/0185
CPCG06F30/30H03K19/018507
Inventor 王林飞刘海南罗家俊韩郑生张宏远
Owner SOI MICRO CO LTD