High-density circuit chip packaging process

Abstract

The invention relates to a high-density circuit chip packaging process, and relates to the technical field of semiconductor packaging processes. The high-density circuit chip packaging process comprises the following steps of: electroplating: electroplating on the front of a copper substrate according to the pattern of a circuit of a chip so as to form an electroplated layer used as the circuit, and electroplating at the back of the copper substrate according to the pattern of an external pin so as to form an external pin electroplated layer; sticking crystal grains and electrifying: sticking crystal grains, and welding a wire among the crystal grains and the welding position of the circuit, so that electric connection is realized; plastically packaging: performing injection moulding on the front of the copper substrate so as to form a plastic protection layer; and manufacturing the external pin: etching the copper substrate at the back of the copper substrate, and removing the part of the copper substrate, which is not covered by the external pin electroplated layer, by etching, wherein the part of the copper substrate, which is covered by the external pin electroplated layer and not etched, and the external pin electroplated layer are used as the external pins.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging. Background technique [0002] In the existing chip packaging process that uses a lead frame as the substrate, the circuit of the chip is etched out by using the copper substrate. If the circuit of the chip is simple and the density is low, there is no problem with this process. However, for chips with complex circuits and high density, the disadvantages of using copper substrates to etch the circuits of the chips are highlighted. If the lines or feet are too dense, the lines need to be made very thin while ensuring that the size does not increase too much, and the etching process is limited by the thick copper bottom and the etching factor, so it is impossible to achieve a small line etching gap , which limits the density of the circuit of the chip, the circuit cannot be designed too densely, and the circuit of the chip cannot be flexibly designed. Contents of the invention ...

AI Technical Summary

Problems solved by technology

[0002] In the existing chip packaging process based on the lead frame, the circuit of the chip is etched out by using the copper substrate. If the circuit of the chip is simple and the density is low, there is no problem with this process.

However, for chips with complex circuits and high density, the disadvantages of using copper substrates to etch the circuits of chips are highlighted.

If the lines or feet are too dense, the lines need to be made very thin while ensuring that the size does not increase too much, and the etching process is limited by the thick copper bottom and the etching factor, so it is impossible to achieve a small line etching gap , which limits the density of the circuit of the chip, the circuit cannot be designed too densely, and the circuit of the chip cannot be designed flexibly

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