Enhanced stacked esd circuit and mixed voltage input and output interface circuit
A stacked and enhanced technology, applied in the direction of circuit devices, emergency protection circuit devices, emergency protection circuit devices for limiting overcurrent/overvoltage, etc., can solve the problem of weak discharge current capacity and achieve enhanced discharge Current capability, increasing current, and increasing the effect of gate voltage
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Embodiment 1
[0097] Such as image 3 As shown, the present embodiment provides an enhanced stacked ESD circuit 2, and the ESD circuit includes:
[0098] an internal ESD bus for providing voltage to said ESD circuit;
[0099] A voltage divider circuit, connected to the internal ESD bus, for dividing the voltage of the internal ESD bus;
[0100] The RC detection circuit is connected with the internal ESD bus, and is used to realize that when the voltage of the internal ESD bus is a normal power-on pulse, the RC detection circuit outputs a high level, and when the voltage of the internal ESD bus is a high-voltage transient pulse, the The RC detection circuit outputs a low level;
[0101] An inverter circuit is connected to the RC detection circuit and the discharge circuit respectively, and is used for inverting the voltage output by the RC detection circuit, thereby controlling the opening and closing of the discharge circuit;
[0102] The bias voltage transmission circuit is connected wi...
Embodiment 2
[0125] Such as Figure 5 As shown, this embodiment provides a mixed voltage input and output interface circuit, which is connected between the chip pin and the external circuit, and the interface circuit includes:
[0126] The ESD protection circuit located on the pins of the chip is connected between the power supply terminal VDD and the ground terminal VSS for ESD protection of the chip;
[0127] The N×VDD input and output buffer circuit is respectively connected to the power supply terminal, the ground terminal and the chip pin, and is used to realize the signal transmission between the chip pin and the external circuit; wherein, the ESD protection circuit includes:
[0128]The second forward-biased diode D2 is connected between one end of the chip pin and the enhanced stacked ESD circuit, and is used to transmit the forward high voltage transient pulse on the chip pin to the enhanced stacked ESD circuit;
[0129] The third reverse-biased diode D3 is connected between the ...
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