5results about How to "Reduce equivalent resistance" patented technology

The application relates to a solar cell device and a preparation method thereof, the device comprising a transparent substrate, a transparent front electrode, a first insulating layer, a photoelectric conversion structure layer, a metal back electrode, a second insulating layer and a front electrode lead-out electrode arranged in sequence; the second insulating layer, the metal back electrode and the photoelectric conversion structure layer are provided with a via hole penetrating to the surface of the transparent front electrode, the front electrode lead-out electrode extends into the via hole, is electrically connected with the transparent front electrode and is electrically isolated from the metal back electrode and the photoelectric conversion structure layer; the front electrode lead-out electrode is used for guiding the carriers collected by the transparent front electrode to the outer layer of the device. Compared with a traditional solar cell, the application breaks through the limitation of the device area on the efficiency, enables the organic solar cell and the perovskite solar cell to still maintain a high efficiency under the condition of area expansion, and provides a feasible technical path for the industrialized production of a large-area flexible solar cell.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

This application provides a light-emitting diode (LED) and a light-emitting device. A first electrode is formed on one side of the first semiconductor layer of the LED. The first electrode has multiple body portions distributed on opposite sides of the LED and multiple extension portions electrically connected to the body portions. The multiple extension portions include main extension portions and secondary extension portions distributed in a first direction and a second direction. This design increases the number of body portions of the first electrode and adaptively increases the number and distribution of the extension portions, thus shortening the current conduction distance, improving current spreadability, and making the current distribution of the LED more uniform. Simultaneously, the increased number of body portions correspondingly increases the number of leads between the LED and external circuits, thereby reducing the equivalent resistance of the LED and ultimately lowering the voltage of the LED package, reducing input power, and thus improving the photoelectric conversion efficiency of the LED.

This invention discloses a frequency tuning method and resonator for a quartz crystal tuning fork oscillator. The method includes: a coating step: cleaning the quartz crystal blank and depositing a base metal layer after cleaning; a coarse tuning step: repeatedly printing conductive paste in the tuning area of ​​the tuning fork arm and curing it to form a printed tuning layer, adjusting the frequency of the tuning fork oscillator to a preset frequency range; and a fine tuning step: performing an excitation test to obtain the current frequency F1, using a laser to perform targeted ablation on the printed tuning layer, stopping when the frequency reaches the target value F2, thus completing the frequency tuning of the quartz crystal tuning fork oscillator. This invention adopts a layered coating architecture, abandoning the full vacuum process, and using a stacked structure of "one-time vacuum coating (base conductive / reflective layer) + two-time printed coating (tuning weight-adding layer)," which solves the problem of material waste and achieves nanometer-level precise frequency locking.

This invention relates to the field of cathode materials for aqueous zinc-ion batteries, and discloses a Ce-α-MnO2 / CNTs nanowire, its preparation method and application, an aqueous zinc-ion battery cathode sheet and its preparation method, and an aqueous zinc-ion battery. The preparation method of Ce-α-MnO2 / CNTs nanowires includes: first mixing multi-walled carbon nanotubes, trivalent cerium salt, and manganese sulfate in the presence of an inorganic solvent to obtain a mixture I; second mixing potassium permanganate solution with the mixture I to obtain product I; subjecting product I to a hydrothermal reaction to obtain product II; and drying product II to obtain Ce-α-MnO2 / CNTs nanowires. The Ce-α-MnO2 / CNTs nanowires of this invention, as a cathode material, have a high specific capacity, can improve the charge and discharge rate of aqueous zinc-ion batteries, and thus enhance the overall performance of aqueous zinc-ion batteries.