Valid data merging method, memory controller and memory storage device

A technology of memory controller and valid data, applied in the direction of memory address/allocation/relocation, etc., can solve the problem of long waiting time for the host system to respond

Active Publication Date: 2017-03-01
PHISON ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the two traditional methods are independent mechanisms, when both need to load the logical address-physical address mapping table into the buffer memory, the same logical address-physical address mapping table may be loaded repeatedly to buffer memory, causing the host system to wait too long for a response

Method used

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  • Valid data merging method, memory controller and memory storage device
  • Valid data merging method, memory controller and memory storage device
  • Valid data merging method, memory controller and memory storage device

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Embodiment Construction

[0094] Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

[0095] figure 1 A host system and a memory storage device are shown according to an exemplary embodiment.

[0096] Please refer to figure 1 , the host system 1000 generally includes a computer 1100 and an input / output (input / output, referred to as: I / O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM for short) 1104 , a system bus 1108 and a data transmission interface 1110 . The input / output device 1106 includes such as figure 2 mouse 1202, keyboard 1204, monitor 1206 and printer 1208. It is important to understand that figure 2 The devices shown are not limited to the i...

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Abstract

The invention provides a valid data merging method, a memory controller and a memory storage device. The method comprises following steps: selecting a first physical erasing unit, and loading a first logic address-physical address mapping table according to a physical address-logic address mapping table. The method further comprises following steps: renewing the first logic address-physical address mapping table according to the physical address-logic address mapping table; and recognizing valid data in the first physical erasing unit according to the physical address-logic address mapping table and the first logic address-physical address mapping table. The method further comprises storing the first logic address-physical address mapping table, copying valid data to a second physical erasing unit and performing erasing operation on the first physical erasing unit. The valid data merging method, the memory controller and the memory storage device have following beneficial effects: delay caused by performing erasing operation on the physical address-logic address mapping table and merging valid data is effectively reduced.

Description

technical field [0001] The invention relates to an effective data combination method for a rewritable non-volatile memory, a memory controller and a memory storage device. Background technique [0002] Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size, no mechanical structure, fast read and write speed, etc., it is most suitable for portable electronic products, such as laptop. A solid state drive is a memory storage device that uses flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years. [0003] The flash memory module has a plurality of physical erasing units and each physical erasing unit has a plurality of physical programming units (physi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
Inventor 叶志刚
Owner PHISON ELECTRONICS
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