Well potential measurement circuit under single particle effect modulation in CMOS process
A single event effect and potential measurement technology, which is applied to circuits, semiconductor/solid-state device testing/measurement, electrical components, etc., can solve problems such as abnormal changes in device logic states, circuit effects, and device damage.
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[0014] The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and cannot be used to limit the protection scope of the present invention.
[0015] like figure 1 As shown in the figure, a single event effect modulation lower well potential measurement circuit in a CMOS process of the present invention is characterized in that it includes a collection module for collecting M (M is a positive integer) well contact potential values, corresponding to N (N is a positive integer) collection module Integer) D flip-flop module and PISO output module of different clock signals CLK;
[0016] The acquisition module for collecting well potential values at different positions, according to the division corresponding to the D flip-flop module, the acquisition module can be set to N first-level times corresponding to different clock ...
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