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Chip package and method for forming the same

A technology of chip package and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problem that the size of the chip package is difficult to further reduce, and achieve the effect of size reduction

Inactive Publication Date: 2017-04-05
XINTEC INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the wafer is picked up and pressed during the bonding process, so the wafer needs to have sufficient thickness to avoid physical damage to the wafer (for example, cracking of the wafer), so that it is difficult to further reduce the size of the chip package.

Method used

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  • Chip package and method for forming the same
  • Chip package and method for forming the same
  • Chip package and method for forming the same

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Embodiment Construction

[0011] The fabrication and use of the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many applicable inventive concepts, which can be embodied in a wide variety of specific forms. The specific embodiments discussed herein are merely specific ways to make and use the invention, and do not limit the scope of the invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present invention, and do not represent any relationship between the different embodiments and / or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer or is separated by one or more other material layers.

[0012] ...

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Abstract

A chip package is provided. The chip package includes a first substrate including a sensing region or device region. The chip package also includes a second substrate. The first substrate is mounted on the second substrate and is electrically connected to the second substrate. The ratio of the thickness of the first substrate to the thickness of the second substrate is in a range from 2 to 8. The size of the chip package can be smaller, further.

Description

technical field [0001] The present invention relates to a chip packaging technology, in particular to a thinned chip package and a manufacturing method thereof. Background technique [0002] The chip packaging process is an important step in the process of forming electronic products. In addition to protecting the chip therein from external environmental pollution, the chip package also provides an electrical connection path between the electronic components inside the chip and the outside world. [0003] The process of making a chip package includes bonding the chip to a circuit board. However, the chip is picked up and pressed during the bonding process, so the chip needs to have sufficient thickness to avoid physical damage to the chip (for example, cracking of the chip), so that it is difficult to further reduce the size of the chip package. [0004] Therefore, it is necessary to find a novel chip package and its manufacturing method, which can solve or improve the abo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/683
CPCH01L21/6835H01L2221/68327H01L2224/02166H01L27/14618H01L27/14627H01L27/14636H01L27/14683H01L2924/00014H01L24/32H01L24/48H01L24/73H01L24/83H01L24/85H01L24/92H01L2221/6834H01L2224/32225H01L2224/48227H01L2224/73265H01L2224/92247H01L2221/68381H01L2224/04042H01L2224/48091H01L2224/45099H01L2224/05599H01L2924/00H01L21/78H01L24/09H01L2224/05022
Inventor 关欣刘沧宇李柏汉
Owner XINTEC INC