LDPC encoder for secondary level full parallel input ring shift left in deep space communication

Abstract

The invention provides a QC-LDPC encoder based on a secondary pipeline in deep space communication. The encoder comprises a sparse matrix and vector multiplier and a vector and high-density matrix multiplier. The sparse matrix and vector multiplier realizes sparse matrix and vector multiplication. The vector and high-density matrix multiplier uses a full parallel input ring shift left mechanism to realize vector and high-density matrix multiplication. The whole coding process is divided into two levels of pipeline. According to the invention, the 8 / 11 bit rate QC-LDPC encoder in a deep space communication system has the advantages of high operating frequency, high throughput and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a QC-LDPC coder with two-stage fully parallel input cyclic left shift in a deep space communication system. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The commun...

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Problems solved by technology

[0006] The existing all-parallel input solution for the 8 / 11 code rate QC-LDPC encoder in the deep space communication standard is as follows: figure 1 As shown, the main disadvantage of this scheme is that the modulo 2 adder has e×b input terminals, and the delay of the addition operation is long, which will cause the encoder to have low operating frequency and low throughput

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