NVM testing reading acceleration method and circuit

Abstract

The invention discloses an NVM testing reading acceleration method and circuit. The circuit comprises an address generation logic for generating an NVM address, an NVM for storing information, a comparison data generation logic for generating expected data, a comparison logic for generating a comparison result, a related register and the like. The method comprises the following steps: in an NVM reading-accelerated test, software is adopted for starting, and hardware automatically executes the work of NVM data reading comparison; the hardware automatically performs calculation according to a software configuration value in the NVM, operates the NVM to read out data, simultaneously calculates the expected data, compares the two pieces of data to obtain the comparison result to determine whether to continue the test or not, can continue comparison of the next address if the result is that the two pieces are equal, and stops the test and outputs the result to the software if the result is that the two pieces are unequal, and then the software can perform analysis and debugging in a manner of reading the register. According to the method, NVM reading and data comparison time can be effectively reduced.

Description

technical field [0001] The invention belongs to the field of test design of integrated circuit chips, in particular to the field of testability design, and can effectively improve the speed of reading and comparing data of NVM memories through internal parallel automatic data comparison. Background technique [0002] Wafer testing plays a very important role in the manufacturing process of semiconductor products. From the time the chip is processed and manufactured to the end customer, it has gone through many different tests to ensure the quality of the product. With the advancement of semiconductor process technology and the gradual increase in design complexity, it has had a huge impact on chip testing costs. The test time becomes longer, which lengthens the chip development cycle; the test cost increases, which makes the cost of the whole chip soar. As the capacity of NVM increases, the test time of NVM increases rapidly, and the time required for data reading and compa...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the problem that NVM consumes a long time in the serial reading of characteristic Pattern during testing, and realizes internal parallel data reading comparison by hardware to improve speed

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