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Nonvolatile semiconductor memory

A non-volatile, semiconductor technology, used in semiconductor devices, static memory, semiconductor/solid-state device manufacturing, etc., to solve problems such as write errors, incorrect writing, and the inability of write current to exceed the write threshold.

Active Publication Date: 2017-05-10
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Therefore, if an access transistor capable of supplying a write current capable of correctly writing to a memory cell with the worst write characteristic (the largest write current) is designed, there may be cases where the memory cell with the best write characteristic (the largest write current) When the memory cell is read, the read current exceeds the write threshold, and an incorrect write occurs
[0006] Also, if an access transistor is designed to supply a read current such that the read current does not exceed the write threshold value when reading the memory cell with the best write characteristic, the memory cell with the worst write characteristic may When writing, the write current cannot exceed the write threshold, and a write error occurs

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0059] figure 2 A first example of the layout of the memory cell array is shown.

[0060] The m substrate regions Sub0 , Sub1 , . . . Sub(m−1) are arranged in the semiconductor substrate and electrically separated from each other. However, m is a natural number of 2 or more. The m substrate regions Sub0, Sub1, . . . Sub(m−1) are, for example, well regions. In addition, the device structure of the memory cell array will be described later.

[0061] The m substrate regions Sub0 , Sub1 , . . . Sub(m−1) include a plurality of unit parts CU-L, CU-R, respectively. Each of the plurality of unit units CU-L and CU-R includes a memory cell MC and an access transistor AT.

[0062] The memory cell MC is, for example, a two-terminal element, and is a variable resistance element whose resistance value changes according to a write current (bidirectional current). The access transistor AT is, for example, a FET (Field Effect Transistor, field effect transistor) having a gate (control te...

no. 2 Embodiment

[0117] The second embodiment is a modified example of the first embodiment. Therefore, in the second embodiment, the same elements as those in the first embodiment are assigned the same reference numerals, and detailed descriptions thereof are omitted.

[0118] Figure 4 A second example of the layout of the memory cell array is shown.

[0119] The difference between the second embodiment and the first embodiment lies in the connection relationship of the switching transistors SW0L, . . . SW(m-1)L.

[0120] That is, one of the source and the drain of the switching transistors SW0L, ... SW(m-1)L is connected to the substrate contact lines CL0, CL1, ... CL(m-1) via the switching transistor SWL, and the switching transistors SW0L, ... SW (m-1) The other of the source and the drain of L is connected to word lines WL0 , WL1 , . . . WL(i-2), WL(i-1).

[0121] According to this example, the potential of the selected word line is applied to the access region (the selected substrate...

no. 3 Embodiment

[0131] The third embodiment is a modified example of the first embodiment. Therefore, in the third embodiment, the same elements as those in the first embodiment are assigned the same reference numerals, and detailed descriptions thereof are omitted.

[0132] Figure 6A as well as Figure 6B A third embodiment of the layout of the memory cell array is shown.

[0133]The difference between the third embodiment and the first embodiment lies in the connection relationship of the switching transistors SW0L, . . . SW(m-1)L, SW0R, . . . SW(m-1)R. That is, the control terminals (gates) of the switching transistors SW0L, . . . SW(m-1)L, SW0R, . i-1) Connection.

[0134] For example, in Figure 6A In the example of , the switching transistors SW0L, ... SW(m-1)L, SW0R, ... SW(m-1)R are controlled on / off by control signals φ0, φ1, ... φ(m-1).

[0135] In addition, in Figure 6B In the example, through the control signal φ0L, φ1L, ... φ(m-1)L, the on / off of the switching transistor...

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Abstract

According to an embodiment of the present invention, nonvolatile semiconductor memory is provided with: a substrate region (Sub(m-1)); a cell unit (CU-L) in the substrate region (Sub(m-1)), said cell unit including a memory cell (MC), and an access transistor (AT), which has a control terminal that is connected to a word line (WL(i-1)), and the substrate region (Sub(m-1)) as a channel, and which supplies a readout current or a write current to the memory cell (MC); and a substrate potential setting circuit, which sets the substrate region (Sub(m-1)) to a first substrate potential when supplying the readout current to the memory cell (MC), and sets the substrate region (Sub(m-1) to a second substrate potential that is different from the first substrate potential when supplying the write current to the memory cell (MC).

Description

technical field [0001] Embodiments relate to nonvolatile semiconductor memories. Background technique [0002] In a nonvolatile semiconductor memory, a trade-off between a write error and a read disturbance at the time of reading becomes a problem. [0003] For example, in a magnetic random access memory which is one of nonvolatile semiconductor memories, the write current tends to decrease in accordance with the improvement in the characteristics of the magnetoresistive element as a memory cell. On the other hand, the read current needs to be smaller than the write current, but the value cannot be sufficiently reduced in order to realize high-speed sensing. As a result, the current difference (margin) between the write current and the read current is reduced. [0004] In addition, a nonvolatile semiconductor memory generally has variations in writing characteristics in that a plurality of memory cells in a memory cell array have different writing currents. However, the w...

Claims

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Application Information

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IPC IPC(8): G11C11/15G11C13/00H01L21/8246H01L27/10H01L27/105
CPCG11C11/1653G11C11/1655G11C11/1657G11C11/1659G11C11/1673G11C11/1675G11C11/1693G11C13/0023G11C13/0026G11C13/0028G11C13/003G11C13/004G11C13/0061G11C13/0069G11C2213/74G11C2213/79H01L28/00G11C11/161G11C11/1695
Inventor 野口纮希高谷聪藤田忍
Owner KIOXIA CORP