A unified staining array scoreboard implementation architecture based on dimt architecture

Abstract

The invention belongs to the field of computer graphic processing hardware, and particularly relates to a uniform dyeing array scoreboard implementation framework based on a DIMT framework. The framework comprises an instruction state table (1), a function unit state table (2), a register state table (3) and state update and relevant detection logic (4). The statistics of a use situation of various resources in an operation process of a dyeing array and instruction analysis for two to-be-emitted instructions of multiple warps can be carried out so as to judge which double instructions corresponding to the warp can be emitted at the moment, so that a stainer array can be guaranteed to correctly and efficiently execute superscale calculation.

Description

technical field [0001] The invention belongs to the field of computer graphics processing hardware, and in particular relates to a unified dyeing array scoreboard realization architecture based on a DIMT architecture. Background technique [0002] The unified colorer array is often superscalar in operation processing. There are dozens of warps to be scheduled and dozens of parallel units to perform operations at the same time. How to efficiently and accurately schedule multiple warps to perform operations on multiple parallel units, Seriously affect the performance and efficiency of superscalar computing. At present, most of the public research is aimed at the research of single-scene and multi-threading, and no research on the scoreboard for multi-scene, multi-thread, and multi-launch has been found. Contents of the invention [0003] Purpose of the invention: [0004] The present invention mainly provides a unified dyeing array scoreboard implementation architecture ba...

AI Technical Summary

Problems solved by technology

[0002] The unified colorer array is often superscalar in operation processing. There are dozens of warps to be scheduled and dozens of parallel units to perform operations at the same time. How to efficiently and accurately schedule multiple warps to perform operations on multiple parallel units, Seriously affects the performance and efficiency of superscalar computing

At present, most of the public research is aimed at the research of single-site multi-threading, and no scoreboard research for multi-site, multi-thread, and multi-launch has been found.

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