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Pcie network system with fail-over capability and operation method thereof

A technology of peripheral components and interconnection network, applied in the field of fast peripheral component interconnection network system, to achieve the effect of reducing service interruption time

Active Publication Date: 2017-05-31
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The main limitation of traditional PCIe architecture is that there is only one active root complex per PCIe domain at any point in time
The result is that no two servers are allowed to coexist in the same PCIe domain

Method used

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  • Pcie network system with fail-over capability and operation method thereof
  • Pcie network system with fail-over capability and operation method thereof
  • Pcie network system with fail-over capability and operation method thereof

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Embodiment Construction

[0046] As used throughout the specification of this application, including the claims, the term "coupled (or connected)" may refer to any means of connection, direct or indirect. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. In addition, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

[0047] The Peripheral Component Interconnect (PCI) standard allows the bus to behave like a bridge that isolates the local processor bus from the peripheral components, al...

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Abstract

A Peripheral Component Interconnect Express (PCIe) network system with fail-over capability and an operation method thereof are provided. The PCIe network system includes a management host, a PCIe switch, a first non-transparent bridge, and a second non-transparent bridge. The upstream port of the PCIe switch is electrically coupled to the management host. The first non-transparent bridge is disposed in the PCIe switch for electrically coupling to the first PCIe port of a calculation host. The first non-transparent bridge can couple the first PCIe port of the calculation host to the management host. The second non-transparent bridge is disposed in the PCIe switch for electrically coupling to the second PCIe port of the calculation host. The second non-transparent bridge can couple the second PCIe port of the calculation host to the management host.

Description

technical field [0001] The present disclosure relates to a Peripheral Component Interconnect Express (hereinafter referred to as PCIe) device, and in particular to a peripheral component interconnect express network system and operation method with failover capability. Background technique [0002] Peripheral Component Interconnect Express (PCIe) is an industry standard computer expansion technology developed by the PCI Special Interest Group (PCI-SIG). PCIe was originally designed as a local bus interconnect technology (local bus interconnect technology), used to connect CPU, GPU and I / O devices in a machine, and has since developed into a point-to-point link (point-to-point links), hop-by-hop flow control, and end-to-end retransmission (end-to-end retransmission) and other features of a fully mature switched network (switched network). PCIe can also be used as a passive backplane interconnect among boards, and as an expansion interface for connecting machines and external...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F13/40
CPCG06F11/22G06F13/4004G06F11/2007G06F11/2028G06F11/2038G06F11/2043G06F11/2097G06F13/4022G06F13/404G06F13/4282G06F11/1417G06F11/1423G06F11/2017G06F11/2033
Inventor 李肇棠涂政君阙志克
Owner IND TECH RES INST
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