Method for extracting thermal resistance of SOI MOS device

A technology of MOS devices and thermal resistance, which is applied in the field of semiconductors, can solve the problems of expensive equipment and achieve the effect of simple cost and simple measurement method
CN106802385AActive Publication Date: 2017-06-06锐立平芯微电子(广州)有限责任公司
4 Cites 2 Cited by

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
锐立平芯微电子(广州)有限责任公司
Publication Date
2017-06-06

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
Patent Text Reader

Abstract

The invention discloses a method for extracting thermal resistance of an SOI MOS device. The method includes the following steps: when a first MOS device is in a non-working state, testing subthreshold slopes of a second MOS device at different temperatures, thereby obtaining subthreshold slope standard data; at a first environment temperature, testing the current subthreshold slope of the second MOS device when the first MOS device is in a working state; determining the current working temperature of the first MOS device according to the current subthreshold slope and the subthreshold slope standard data; and determining the thermal resistance of the first MOS device according to a difference value of the current working temperature and the first environment temperature. The method provided by the invention solves the technical problem in the prior art that equipment is expensive when a PIV method is utilized to measure thermal resistance. A simple and low cost thermal resistance measuring method is realized.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a thermal resistance extraction method of an SOI MOS device. Background technique

[0002] Silicon-On-Insulator (SOI) technology introduces a layer of Buried Oxide (BOX) between the top layer of silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, it can be said that SOI will likely become a deep submicron low-voltage , The mainstream technology of low-power integrated c...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More