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Method and device for rounding decimal addition results

An addition and decimal technology, which is applied in the field of rounding of decimal addition results, can solve the problems of floating-point multiplier-adder or fixed-point decimal multiplier-adder that consume a lot of resources and cannot get results quickly, so as to achieve quick judgment and improve calculation efficiency.

Inactive Publication Date: 2019-04-23
青岛专用集成电路设计工程技术研究中心
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention discloses a method for rounding the result of decimal addition to solve the problem that floating-point multiply-adders or fixed-point decimal multiply-adders in existing high-performance processors consume a lot of resources and cannot obtain results quickly

Method used

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  • Method and device for rounding decimal addition results
  • Method and device for rounding decimal addition results

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Embodiment Construction

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0030] see figure 1 Shown is the flow chart of the first embodiment of the rounding method of decimal addition results disclosed in the present invention. The present invention aims to give calculation results faster, avoid parallel addition and carry selection operations at the same time, and reduce the number of adders used. resource. Specific...

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Abstract

The invention provides a rounding method for decimal addition result. The method comprises the following steps of defining the parameter of an adding device, then according to the adding device, inputting the operand and setting a carry transmission factor, a carry generation factor and a carry cancel factor; utilizing the carry transmission factor and the carry cancel factor to judge and calculate the result of handling of lower part, and utilizing the carry transmission factor and the carry generation factor to judge and calculate the result of handling of higher part to obtain the rounding output. At the same time the invention also discloses a rounding device for decimal addition result. The method is capable of replacing the method of utilizing two independent adding device to calculate in the prior art through handling the lower calculation and higher carry prediction separately. The test show that the rounding method for decimal addition result is capable of effectively improving the calculating efficiency in the prior art, and in the operation of floating point multiplying device or fix-point decimal, the method is capable of judging the lower result much more rapidly so that the following operation can be started much more fast.

Description

technical field [0001] The invention relates to the technical fields of data processing and application-specific integrated circuits, in particular to a method and device for rounding decimal addition results. Background technique [0002] The rounding (Round) operation on the result of the adder, also known as the rounding operation, is one of the common result processing operations, and there are similar designs in almost all processors. In a floating-point adder, if the exponents of the two input numbers of the adder are different, the mantissa of the input number with a smaller exponent is generally shifted to the right and then operated with another input number. The shifted bits need to be rounded up before outputting the result. According to the rounding standard of IEEE, whether to carry the lower bit up needs to comprehensively consider all the shifted bits, the least significant bit and the second least significant bit of the result of the adder. In this case, th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/485
CPCG06F7/485
Inventor 周沈刚李任伟
Owner 青岛专用集成电路设计工程技术研究中心
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