Static random access memory and operation method thereof

Abstract

The invention discloses a static random access memory and an operation method thereof. The static random access memory comprises the following components: a latch unit, which is connected between a first node and a second node; a first pass-transistor, wherein a first terminal of the first pass-transistor is connected to a first bit line, a second terminal is connected to the first node, a first gate is connected to a first word line, and a second gate is connected to a second word line; a second pass-transistor, wherein a first terminal of the second pass-transistor is connected to a second bit line, a second terminal is connected to a second bit line, a first gate is connected to the first word line, and a second gate is connected to the second word line; the pass-transistor comprises two working modes, such as electron conduction or hole conduction, the working mode of the pass-transistor, such as electron conduction or hole conduction, can be selected by adjusting level of the first word line and the second word line, and conducting or breaking state of the pass-transistor in a corresponding working mode can be controlled. The pass-transistor has adjustable driving capability during conduction, and has very low leakage current during breaking, so that the power consumption of the latch unit during data hold is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random access memory (SRAM) and an operation method thereof. Background technique [0002] For a long time, the field of semiconductor integrated circuits has been developing continuously in accordance with the law of Moore's Law. Among them, with the advancement of technology, the feature size of CMOS devices in SRAM has shrunk from micron level to deep submicron level. However, when the device is reduced to the nanometer scale, it brings many severe challenges to SRAM, such as increased process complexity, degradation of short channel characteristics, decreased reliability, increased leakage current and power consumption, etc. Among them, the short-channel effect and various leakage currents (and the resulting power consumption) in the device have become important obstacles to the development of SRAM technology. Usually, in the design of SRAM memory, it is dif...

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Problems solved by technology

Usually, it is difficult to optimize the performance indicators such as capacity, speed, area and power consumption in the design of SRAM memory at the same time to meet various application requirements. The performance limitation of power consumption also makes it to some extent Further miniaturization of CMOS devices in SRAM is becoming increasingly difficult

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