Linear interpolation method and apparatus for fixed interpolation multiple of digital signal

A digital signal, linear interpolation technology, applied in electrical digital data processing, measurement devices, digital variable display and other directions, can solve the problems of large computational load, high circuit implementation cost, consumption of FPGA resources, etc., to achieve fast parallel operation, real-time Good performance and the effect of reducing FPGA resources

Inactive Publication Date: 2017-06-27
SHENZHEN CITY SIGLENT TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The existing technology needs to repeatedly use the multiplication operation, and the multiplication operation has a very large amount of calculation in the software operation, consumes a lot of FPGA resources in the hardware operation, and the circuit implementation cost is relatively high

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  • Linear interpolation method and apparatus for fixed interpolation multiple of digital signal
  • Linear interpolation method and apparatus for fixed interpolation multiple of digital signal
  • Linear interpolation method and apparatus for fixed interpolation multiple of digital signal

Examples

Experimental program
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Effect test

Embodiment 1

[0078] The linear interpolation method of the fixed interpolation multiple provided by the embodiment of the present application includes:

[0079]Step 100, the original data y of the digital signal to be processed 0 、y * Perform addition to get Δy=y * -y 0 .

[0080] Step 101, generate the interpolation multiple data c of the digital signal to be processed by the fixed interpolation multiple to be interpolated i , according to c i value, the controller 5 controls the shift register 4 to perform a corresponding shift operation on Δy, each shift generates a shifted data in sequence, and stores the shifted data in the memory 6 .

[0081] For example, for 8bit data, if a linear interpolation of 20 times is performed, like Figure 7 As shown, calculate the first interpolated value y 1 hour, The shift register 4 carries out a 4-bit shift and a 6-bit shift to Δy to generate shift data (Δy>>4) and (Δy>>6) respectively, which are stored in the memory 6; and so on, according...

Embodiment 2

[0091] The linear interpolation method with a fixed interpolation multiple provided in the embodiment of the present application includes:

[0092] Step 200, the original data y of the digital signal to be processed 0 、y * Perform addition to get Δy=y * -y 0 .

[0093] Step 201, generate the interpolation multiple data c of the digital signal to be processed by the fixed interpolation multiple to be interpolated i , the shift register 4 performs an n-bit shift operation on Δy, generates corresponding shift data for each bit shift, and stores the shift data in the memory 6, n+1 is the bit width of the digital signal to be processed, n = 2 η -1, n is a positive integer greater than or equal to 3.

[0094] For example, for 8bit data, if a linear interpolation of 20 times is performed, such as Figure 8 As shown, the shift register 4 shifts Δy by 7 bits, and generates corresponding shift data for each bit shifted, and shifts the shift data (Δy>>0) to (Δy>>7 ) are all store...

Embodiment 3

[0105] The linear interpolation method with a fixed interpolation multiple provided in the embodiment of the present application includes:

[0106] Step 300, the original data y of the digital signal to be processed 0 、y * Perform addition to get Δy=y * -y 0 .

[0107] Step 301, generate the interpolation multiple data c of the digital signal to be processed by the fixed interpolation multiple to be interpolated i , according to c i The controller 5 controls different shift registers to perform corresponding shift operations on Δy at the same time.

[0108] For example, for 8bit data, if a linear interpolation of 20 times is performed, like Figure 9 As shown, calculate the first interpolated value y 1 hour, The shift register 44 shifts Δy by 4 bits to obtain shifted data (Δy>>4), and at the same time, the shift register 46 shifts 6 bits to Δy to obtain shifted data (Δy>>6); accordingly By analogy, according to c 1 ~ c 19 , perform the corresponding shift operati...

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Abstract

The invention discloses a linear interpolation apparatus for a fixed interpolation multiple. The apparatus comprises a first adder, a shift register, a memory, a second adder, a third adder and a controller connected in sequence, wherein the controller is connected with the shift register and the memory; the controller controls the shift register to perform shift operation and read multiple pieces of shift data from the memory; the shift register, the memory and the second adder are used to perform a series of shift operation and addition operation to realize multiplication operation, so that the use of a multiplier is avoided, the FPGA resource consumption and the operation amount are reduced, the operation speed is increased, and the timeliness of linear interpolation calculation is improved; and parallel operation also can be quickly carried out, linear interpolations are obtained in parallel, and the operation is quick and high in timeliness. Correspondingly, the invention discloses a linear interpolation method for the fixed interpolation multiple.

Description

technical field [0001] The application relates to the field of electronic instruments, and in particular, to a linear interpolation method and device for a digital signal with a fixed interpolation multiple. Background technique [0002] Linear interpolation of digital signals is a commonly used multi-sampling rate digital signal processing method. By extending a shorter low-speed digital signal sequence into a longer high-speed digital signal sequence, it can obtain better time and amplitude resolution and resolution. Accuracy, widely used in test and measurement, software-defined radio, wireless communication. For example, in a digital oscilloscope, linear interpolation is provided to convert the digital signal to be processed with a lower time resolution, which is sampled and converted by the oscilloscope, into a digital signal to be processed with a higher time resolution, and displayed as a waveform on the screen. The user zooms in to see details. [0003] For a linea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/05G06T11/20G01R13/02
CPCG06F3/05G01R13/0209G01R13/029G06T11/203
Inventor 宋民李振军王永添
Owner SHENZHEN CITY SIGLENT TECH
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