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Semiconductor package and manufacturing method thereof

A packaging and semiconductor technology, used in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc.

Active Publication Date: 2017-06-30
SAMSUNG SEMICON CHINA RES & DEV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At such a temperature, the substrate 101, the chip, and the encapsulation layer 103 having different thermal expansion coefficients are bonded to each other, so that when the temperature drops to room temperature, the shrinkage of the encapsulation layer 130 causes the substrate 110 to be recessed along the surface on which the chip is mounted. (see figure 1 ), or cause the substrate 110 to protrude along the surface on which the chip is mounted (see figure 2 ) in the direction of warpage

Method used

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  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof

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Embodiment Construction

[0028] Embodiments of the invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will be directed to the The concept of embodiments of the present invention is fully conveyed to those of ordinary skill in the art. In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it will be apparent to those skilled in the art that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components and circuits have been described at a relatively high level, without detail, in order to a...

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Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, at least one chip arranged on the substrate, an encapsulation layer which is arranged on the substrate and encloses at least one chip, at least one grid portion which is arranged in the encapsulation layer, and a number of open main body parts which are defined by a first rib and a second rib.

Description

[0001] This application is a divisional application of a patent application with an application date of July 29, 2015 and an application number of 201510454059.2, entitled "Semiconductor Package and Method of Manufacturing the Semiconductor Package". technical field [0002] Exemplary embodiments of the present invention relate to the field of semiconductor packaging, and in particular, to a semiconductor package and a method of manufacturing the same. Background technique [0003] At present, in a semiconductor package, due to the different Coefficient of Thermal Expansion (CTE) of each element in the semiconductor package, the semiconductor package may be warped, which in turn affects the subsequent mounting process and process of the substrate. cutting process. For example, when a semiconductor chip is encapsulated on a substrate using an encapsulation material such as epoxy, the semiconductor package may warp due to thermal expansion and contraction of the encapsulation ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L21/50
CPCH01L23/3121H01L24/97H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2924/3511H01L2924/00012H01L2224/97H01L2924/15311H01L2924/3025H01L2224/85H01L2924/00
Inventor 顾立群
Owner SAMSUNG SEMICON CHINA RES & DEV
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