Semiconductor package and manufacturing method thereof

Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, at least one chip arranged on the substrate, an encapsulation layer which is arranged on the substrate and encloses at least one chip, at least one grid portion which is arranged in the encapsulation layer, and a number of open main body parts which are defined by a first rib and a second rib.

Description

[0001] This application is a divisional application of a patent application with an application date of July 29, 2015 and an application number of 201510454059.2, entitled "Semiconductor Package and Method of Manufacturing the Semiconductor Package". technical field

[0002] Exemplary embodiments of the present invention relate to the field of semiconductor packaging, and in particular, to a semiconductor package and a method of manufacturing the same. Background technique

[0003] At present, in a semiconductor package, due to the different Coefficient of Thermal Expansion (CTE) of each element in the semiconductor package, the semiconductor package may be warped, which in turn affects the subsequent mounting process and process of the substrate. cutting process. For example, when a semiconductor chip is encapsulated on a substrate using an encapsulation material such as epoxy, the semiconductor package may warp due to thermal expansion and contraction of the encapsulation ...

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