A method for realizing an SoC verification interaction mechanism

Abstract

The invention provides a method for realizing an SoC verification interaction mechanism. The method is characterized in that operations and monitoring for a specific register are separated, and an interaction interface module, a monitor module and an event task module are added for implementation; a C program, the monitor module and an RTL are connected and achieve data interaction via the interaction interface module; the interaction interface module achieves packaging of AHB signals; the monitor module monitors AHB bus signals packaged by the interaction interface module in real time, and when monitoring that an operation to a preset register is present in the AHB bus, maps the operation as a specific event example; the event task module is used for definition and management of specifically executed operations of event examples. An operation of register writing of a CPU is converted to System Verilog business and business is used to control a flow in upper layer test cases, so that the problems of inconvenient use and poor portability and reusability of the conventional method are solved.

Description

technical field [0001] The invention relates to the field of chip design and manufacture, in particular to a method for realizing a novel interaction mechanism for SoC verification. Background technique [0002] With the rapid development of process capability and design capability, in order to meet the requirements of the embedded system market for cost, function and power consumption, SoC technology has become a development trend. SoC technology is supported by ultra-deep submicron process and IP (Intellectual Property) core multiplexing, and its design concept is completely different from traditional design concept. In SoC design, what the designer faces is no longer the circuit chip; but the IP module library that can realize the design function. SoC design cannot start from scratch, the design should be based on a higher foundation, and the existing IP core should be used for design reuse. The system-level chip design technology based on the IP core makes the design m...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that it has poor versatility and portability, and in SoC's UVM (Universal Verification Methodology is a verification platform development framework with SystemVerilog class library as the main body, verification engineers can use its reusable components to build functional verification with standardized hierarchies and interfaces. Environment) verification is inconvenient to use

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