Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes channel layers disposed over a substrate, a source / drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source / drain region. The semiconductor wire in the source / drain regions is wrapped around by a second semiconductor material.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 261,267, filed November 30, 2015, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention relate to semiconductor integrated circuits, and more particularly, to semiconductor devices having a gate-all-around structure and methods of manufacturing the same. Background technique [0004] As the semiconductor industry enters nanotechnology process nodes in the pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have given rise to applications such as the Multi-Gate FinFET (Multi-Gate FinFET) FET) including fin FET (Fin FET) and gate all around (GAA) FET). In a Fin FET, the gate electrode is adjacent to three sides of the channel region, with a gate dielectric layer interposed between the gate electrode and ...

AI Technical Summary

Problems solved by technology

Unfortunately, on the fourth side, the bottom of the channel is far from the gate electrode and thus not under the tight control of the gate

Images