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Dual rail memory, memory macro and associated hybrid power supply method

A memory, memory array technology, used in memory macro and hybrid power supply, dual-rail memory field

Active Publication Date: 2017-08-15
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This leakage power is becoming a significant factor in the total power consumption in the memory

Method used

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  • Dual rail memory, memory macro and associated hybrid power supply method
  • Dual rail memory, memory macro and associated hybrid power supply method
  • Dual rail memory, memory macro and associated hybrid power supply method

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Embodiment Construction

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming a first part over or on a second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include an additional part formed between the first part and the second part. An embodiment in which the first part and the second part are not in direct contact. Also, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] In addition, for the convenience of descri...

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Abstract

A dual rail memory operable at a first voltage and a second voltage is disclosed, and the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of semiconductor technologies, and more particularly, to dual-rail memories, memory macros, and hybrid power supply methods. Background technique [0002] Memory devices are subject to the well known phenomenon of leakage power. Typically, logic devices in the peripheral memory array and core memory array dissipate leakage power whenever the memory is powered on. Leakage power dissipation in memory devices increases as technology continues to shrink device dimensions below sub-nanometer geometries. This leakage power is becoming a significant factor in the overall power consumption in memory. [0003] One way to reduce leakage power is to reduce the supply voltage of the memory device. However, the voltage level of a bit cell in a memory needs to be maintained at a minimum voltage specification for retention, while a peripheral portion of a memory device may operate below a certain v...

Claims

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Application Information

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IPC IPC(8): G11C5/14G11C7/12G11C8/08
Inventor 张琮永郑基廷李政宏廖宏仁迈克尔·克林顿
Owner TAIWAN SEMICON MFG CO LTD