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Shifting register, driving method thereof, gate drive circuit and display device

A shift register and drive signal technology, applied in static memory, digital memory information, instruments, etc., can solve problems affecting the stability of the shift register, the potential instability of the drive signal output terminal, and the noise of the scanning signal

Active Publication Date: 2017-08-25
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] An embodiment of the present invention provides a shift register, its driving method, a gate driving circuit and a display device to solve the problem in the prior art that the pull-down node is in a floating state for a long time after the reset phase, causing the drive signal to output The potential of the terminal is unstable, resulting in a large noise in the output scan signal, which affects the stability of the output of the shift register.

Method used

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  • Shifting register, driving method thereof, gate drive circuit and display device
  • Shifting register, driving method thereof, gate drive circuit and display device
  • Shifting register, driving method thereof, gate drive circuit and display device

Examples

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Effect test

Embodiment 1

[0088] by Figure 3a The structure of the shift register shown is taken as an example to describe its working process, in which Figure 3a In the shift register shown, the potential of the first reference signal terminal VGL is low potential, and the potential of the second reference signal terminal VGH is high potential. The corresponding input and output timing diagram is as follows Figure 5a Shown, specifically, select as Figure 5a There are four stages in the shown input and output timing diagrams: T1 stage, T2 stage, T3 stage and T4 stage.

[0089] In the T1 stage, Input=0, CK1=0, CK2=1, CK3=1.

[0090] Since CK1=0, both the first switch transistor M1 and the fourth switch transistor M4 are turned on. The turned-on first switch transistor M1 provides the low potential signal of the first reference signal terminal VGL to the pull-down node B, so the potential of the pull-down node B is low. Since the potential of the pull-down node B is a low potential, the seventh s...

Embodiment 2

[0102] by Figure 4a The structure of the shift register shown is taken as an example to describe its working process, in which Figure 4a In the shift register shown, the potential of the first reference signal terminal VGL is low potential, and the potential of the second reference signal terminal VGH is high potential. The corresponding input and output timing diagram is as follows Figure 5a Shown, specifically, select as Figure 5a There are four stages in the shown input and output timing diagrams: T1 stage, T2 stage, T3 stage and T4 stage.

[0103] In the T1 stage, Input=0, CK1=0, CK2=1, CK3=1. Since the eighth switch transistor M8 is turned on under the control of the first reference signal terminal VGL, the signal of the pull-up node A can be provided to the control electrode of the sixth switch transistor M6 to turn on the sixth switch transistor M6. The rest of the working process is basically the same as the working process of the T1 stage in the first embodimen...

Embodiment 3

[0112] by Figure 3b The structure of the shift register shown is taken as an example to describe its working process, in which Figure 3b In the shift register shown, the potential of the first reference signal terminal VGL is high potential, and the potential of the second reference signal terminal VGH is low potential. The corresponding input and output timing diagram is as follows Figure 5b Shown, specifically, select as Figure 5b There are four stages in the shown input and output timing diagrams: T1 stage, T2 stage, T3 stage and T4 stage.

[0113] In the T1 stage, Input=1, CK1=1, CK2=0, CK3=0.

[0114] Since CK1=1, both the first switch transistor M1 and the fourth switch transistor M4 are turned on. The turned-on first switch transistor M1 provides the high potential signal of the first reference signal terminal VGL to the pull-down node B, so the potential of the pull-down node B is high. Since the potential of the pull-down node B is a high potential, the sevent...

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Abstract

The invention discloses a shifting register, a driving method thereof, a gate drive circuit and a display device. The shifting register comprises an input module, a first control module, a second control module and an output module. With related matching of the four modules, namely, the input module, the first control module, the second control module and the output module, the floating state of a pull-down node can be shortened, and the influence of electric leakage on potential of the pull-down node can be reduced after effective pulse signals of scanning signals are output from a driving signal output end, accordingly, noise of the output scanning signals is reduced, and the output stability of the shifting register is improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register, a driving method thereof, a gate driving circuit and a display device. Background technique [0002] With the rapid development of display technology, the display panel is more and more developed towards the direction of high integration and low cost. Among them, the gate driver on array (Gate Driver on Array, GOA) technology integrates the thin film transistor (Thin Film Transistor, TFT) gate switching circuit on the array substrate of the display panel to form a scan drive for the display panel, so that the gate driver can be omitted. The wiring space of the Bonding area of ​​the integrated circuit (Integrated Circuit, IC) and the fan-out (Fan-out) area can not only reduce the product cost in terms of material cost and manufacturing process, but also enable the display panel to achieve Beautiful design with symmetry on both sides and narrow borders; moreover...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36G11C19/28
CPCG09G3/3674G09G2310/0286G11C19/28
Inventor 张盛鹉
Owner BOE TECH GRP CO LTD
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