Automatic design method, device and optimization method for neural network processor

Abstract

Disclosed are an automated design method and system for a neural network processor, comprising a neural network model realized by means of a hardware circuit. The method comprises: acquiring a descriptor file of the neural network model and a hardware resource constraint parameter of a target hardware circuit; establishing mapping between a structure of the neural network model and the target hardware circuit, and a control instruction stream and an address access stream corresponding to the neural network model; and then generating, according to the mapping and the control instruction stream and the address stream, a hardware descriptor language code of a neural network processor corresponding to the neural network model, so as to realize the hardware circuit of the neural network processor on the target hardware circuit. The system and method realize an automated design of a neural network processor, shorten the designing cycle of the neural network processor, adapt to the characteristics of the rapid update of network models in neural network technology and the requirement of high operating speed.

Description

technical field [0001] The invention relates to the technical field of neural network processor architecture, in particular to an automatic design method, device and optimization method for neural network processors. Background technique [0002] The rapid development of deep learning and neural network technology provides new solutions for large-scale data processing tasks. Various new neural network models have excellent performance in dealing with complex and abstract problems. New applications in the field emerge in an endless stream. [0003] At present, the real-time task analysis using deep neural networks mostly relies on large-scale high-performance processors or general-purpose graphics processors. These devices have high cost and high power consumption. When they are applied to portable smart devices, they have large circuit scale, high energy consumption and expensive products. And so on a series of questions. Therefore, for energy-efficient real-time processin...

AI Technical Summary

Problems solved by technology

Under the same process conditions, ASIC chips run fast and consume low power consumption, but the design process is complicated, the casting cycle is long, and the development cost is high, which cannot adapt to the characteristics of rapid update of neural network models; FPGA has the characteristics of flexible circuit configuration and short development cycle. features, but the running speed is relatively low, and the hardware overhead and power consumption are relatively large

No matter which of the above hardware acceleration technologies is used, it is necessary for the neural network model and algorithm developers to understand the network topology and data flow mode while mastering the hardware development technology, including processor architecture design, hardware code writing, simulation verification, layout and wiring, etc. , these technologies are more difficult to develop for high-level application developers who focus on researching neural network models and structural design, but do not have hardware design capabilities

Images