Chip encapsulation structure and circuit structure

Abstract

The invention provides a chip encapsulation structure and a circuit structure. The chip encapsulation structure comprises at least two chips, a connection part, multiple second welding balls and a substrate; the active surface of each chip in the at least two chips is positioned in the same plane; the active surface of each chip comprises a first area and a second area; multiple first bonding pads are arranged in the first area; at least one second bonding pad is arranged in the second area; the at least two chips comprise a first chip and a second chip, which are adjacent; multiple first metal wires are distributed in the connection part; both two ends of each first metal wire are exposed on the first surface of the connection part; one end of each first metal wire is connected with one first bonding pad of the first chip; the other end of each first metal wire is connected with one first bonding pad of the second chip; each second bonding pad of the first chip and the second chip is connected with the upper surface of the substrate through a second welding ball; and the upper surface of the substrate is towards the active surface of the chip. By means of the chip encapsulation structure and the circuit structure provided by the invention, the chip encapsulation efficiency is increased.

Description

technical field [0001] The present application relates to the technical field of chip packaging, in particular to a chip packaging structure and a circuit structure. Background technique [0002] As the amount of data to be transmitted between chips increases, more and more connecting wires between chips are required. Since the volume of the chip is small, and the packaging volume of the chip cannot be too large, a relatively high process is required to realize the connection between the chips. [0003] At present, the interconnection between multiple chips is generally realized by a technology of disposing a wafer on a substrate and stacking chips on the wafer (Chip on Wafer on Substrate, CoWoS). Specifically, a plurality of chips are arranged on the upper surface of the adapter board. Since the upper surface of the adapter board is provided with metal wiring, the plurality of chips can be interconnected through the metal wiring on the upper surface of the adapter board. ...

AI Technical Summary

Problems solved by technology

[0004] However, in the above process, due to the complicated process of TSV technology, the chip packaging process is complicated, resulting in low efficiency of chip packaging

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