Elevator safety control device and elevator safety control method
A safety control and elevator technology, which is applied in transportation, packaging, elevators, etc., can solve problems such as undetectable timer abnormality, elevator inoperability, etc., and achieve the effect of ensuring soundness and usability
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Embodiment approach 1
[0021] figure 1 It is an overall configuration diagram of an elevator safety control device according to Embodiment 1 of the present invention. The safety control device 10 according to Embodiment 1 is configured to include a first CPU (Central Processing Unit: central processing unit) 1 and a second CPU 2 which are duplexed. Although not shown, each of the first CPU 1 and the second CPU 2 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a clock, a watchdog timer, a bus, and the like.
[0022] The first CPU 1 and the second CPU 2 are connected by a communication line, and by comparing calculation results with each other, CPU failure diagnosis is performed. Furthermore, the safety control device 10 executes a safety control function, a self-diagnosis function, and a timer diagnosis function based on software respectively installed in the first CPU 1 and the second CPU 2 .
[0023] The 1st CPU 1 and the 2nd CPU 2 respectively receive the signal from the safety-...
Embodiment approach 2
[0076] Figure 4 It is an overall configuration diagram of an elevator safety control device according to Embodiment 2 of the present invention. The safety control device 10 of the second embodiment is different from that of the first embodiment figure 1 The difference in the structure compared with the above is that the timer 5, the timer 6, and the timer comparison unit 7 are provided outside the first CPU 1 and the second CPU 2. Therefore, the following description will focus on such structural differences.
[0077] Such as Figure 4 As shown, the safety control device 10 according to Embodiment 2 is provided with two timers 5 and 6 and a clock (not shown) outside the first CPU 1 and the second CPU 2 . The timers 5 and 6 are constituted by a logic circuit having a counter and a comparator, and perform a counting operation by counting clock pulses.
[0078] And the timer 5 starts and stops the counting operation according to the instruction from the first CPU 1, sets the...
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