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Array substrate, display panel and display device

An array substrate and substrate technology, applied in nonlinear optics, instruments, optics, etc., can solve the problems of affecting display quality, difficult impedance matching, and large impedance difference between Metal1 and Metal2

Active Publication Date: 2017-09-01
XIAMEN TIANMA MICRO ELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the large impedance of Metal1 and the large impedance difference between Metal1 and Metal2, the impedance between Metal1 and Metal2 is not easy to match, which affects the display quality

Method used

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  • Array substrate, display panel and display device
  • Array substrate, display panel and display device
  • Array substrate, display panel and display device

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Embodiment Construction

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

[0034] Figure 1a It is a schematic diagram of the plane structure of the existing fan-out routing layout; Figure 1b for Figure 1a Schematic diagram of the cross-sectional structure along A1-A2. The fan-out line is located in the non-display area of ​​the display panel, adopts a two-layer metal fan-out line structure, and is electrically connected to a signal line (such as a data line, a gate line, and a touch line, etc.) in the display area of ​​the display panel, such as Figure 1a with Figure 1b As shown, t...

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Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises a substrate; multiple grid lines, multiple data lines and multiple touch routing lines are arranged in a display region of the substrate; multiple first fan-out routing lines and multiple second fan-out routing lines are arranged in a fan-out region of the substrate and electrically connected with signal lines of the display region; any kind of signal lines comprises the first kind of signal lines and the second kind of signal lines, at least part of the first kind of signal lines is electrically connected with the first fan-out routing lines, and at least part of the second kind of signal lines is electrically connected with the second fan-out routing lines; the first fan-out routing lines comprise first fan-out routing line sections, the first fan-out routing line sections and the data lines are arranged on the same layers and made of the same materials, the second fan-out routing lines comprise second fan-out routing line sections, and the second fan-out routing line sections and the touch routing lines are arranged on the same layers and made of the same materials. The difference between the impedance of the fan-out region and the impedance between the fan-out routing lines is reduced, and the display quality is improved.

Description

technical field [0001] Embodiments of the present invention relate to display technologies, and in particular to an array substrate, a display panel and a display device. Background technique [0002] In the display product design of the embedded touch display technology (Touch Embed Display, TED), the wiring from the output of the driver chip to the effective display area is defined as a fan-out wiring. There are generally two types of existing fan-out routing: a single-layer metal fan-out routing structure and a two-layer metal fan-out routing structure. [0003] At present, the single-layer metal fan-out wiring structure is adopted. Taking the resolution of full HD as an example: 1080 fan-out wirings are required on the source side, and 1080 metal wirings are required. At this time, the adjacent metal wiring must be considered. The distance between lines prevents short circuit of adjacent metal traces due to exposure limitation, then the corresponding fan-out area will h...

Claims

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Application Information

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IPC IPC(8): G02F1/1362
CPCG02F1/136286
Inventor 骆晓东
Owner XIAMEN TIANMA MICRO ELECTRONICS
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